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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.14 2002/10/17 18:50:00 simont
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// cahnge interface to instruction rom
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//
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// Revision 1.13 2002/09/30 17:33:59 simont
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// Revision 1.13 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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//
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//
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//
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//
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| Line 185... |
Line 188... |
//
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//
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// comp_sel select source1 and source2 to compare
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// comp_sel select source1 and source2 to compare
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// eq result (from comp1 to decoder)
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// eq result (from comp1 to decoder)
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// wad2, wad2_r write to accumulator from destination 2
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// wad2, wad2_r write to accumulator from destination 2
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wire [1:0] comp_sel;
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wire [1:0] comp_sel;
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wire eq, wad2, wad2_r;
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wire eq, wad2, wad2_r, nop;
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//
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//
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// bit_addr bit addresable instruction
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// bit_addr bit addresable instruction
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// bit_data bit data from ram to ram_select
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// bit_data bit data from ram to ram_select
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// bit_out bit data from ram_select to alu and cy_select
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// bit_out bit data from ram_select to alu and cy_select
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wire bit_addr, bit_data, bit_out, bit_addr_r;
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wire bit_addr, bit_data, bit_out, bit_addr_r;
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//
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//
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// p parity from accumulator to psw
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// p parity from accumulator to psw
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wire p;
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wire p, pc_wait;
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wire b_bit, acc_bit, psw_bit, int_bit, port_bit, uart_bit;
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wire b_bit, acc_bit, psw_bit, int_bit, port_bit, uart_bit;
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//
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//
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//registers
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//registers
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| Line 233... |
Line 236... |
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//
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//
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//program counter
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//program counter
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oc8051_pc oc8051_pc1(.rst(rst), .clk(clk), .pc_out(pc), .alu({des2,des1}),
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oc8051_pc oc8051_pc1(.rst(rst), .clk(clk), .pc_out(pc), .alu({des2,des1}),
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.pc_wr_sel(pc_wr_sel), .op1(op1_n), .op2(op2_n), .op3(op3_n), .wr(pc_wr),
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.pc_wr_sel(pc_wr_sel), .op1(op1_n), .op2(op2_n), .op3(op3_n), .wr(pc_wr),
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.rd((rd && !(istb_o && !iack_i))), .intr(intr));
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.rd((pc_wait && !(istb_o && !iack_i))), .intr(intr));
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//
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//
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// decoder
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// decoder
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oc8051_decoder oc8051_decoder1(.clk(clk), .rst(rst), .op_in(op1_n), .ram_rd_sel(ram_rd_sel),
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oc8051_decoder oc8051_decoder1(.clk(clk), .rst(rst), .op_in(op1_n),
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.ram_wr_sel(ram_wr_sel), .bit_addr(bit_addr), .src_sel1(src_sel1), .wr_xaddr(wr_xaddr),
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.ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel), .bit_addr(bit_addr),
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.src_sel2(src_sel2), .src_sel3(src_sel3), .alu_op(alu_op), .psw_set(psw_set),
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.src_sel1(src_sel1), .wr_xaddr(wr_xaddr), .src_sel2(src_sel2),
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.imm_sel(imm_sel), .cy_sel(cy_sel), .wr(wr), .pc_wr(pc_wr), .pc_sel(pc_wr_sel),
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.src_sel3(src_sel3), .alu_op(alu_op), .psw_set(psw_set),
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.comp_sel(comp_sel), .eq(eq), .rom_addr_sel(rom_addr_sel), .ext_addr_sel(ext_addr_sel),
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.imm_sel(imm_sel), .cy_sel(cy_sel), .wr(wr), .pc_wr(pc_wr),
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.wad2(wad2), .rd(rd), .we_o(we_o), .reti(reti), .rmw(rmw), .stb_o(stb_o), .ack_i(ack_i),
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.pc_sel(pc_wr_sel), .comp_sel(comp_sel), .eq(eq),
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.istb(istb), .ea(ea && ea_int), .iack(iack_i));
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.rom_addr_sel(rom_addr_sel), .ext_addr_sel(ext_addr_sel),
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.wad2(wad2), .rd(rd), .we_o(we_o), .reti(reti), .rmw(rmw),
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.stb_o(stb_o), .ack_i(ack_i), .istb(istb), .ea(ea && ea_int),
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.iack(iack_i), .pc_wait(pc_wait), .nop(nop));
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//
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//
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// ram read and ram write select
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// ram read and ram write select
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| Line 365... |
Line 371... |
//
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//
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//
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//
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oc8051_op_select oc8051_op_select1(.clk(clk), .rst(rst), .ea(ea), .ea_int(ea_int), .op1_i(op1_i),
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oc8051_op_select oc8051_op_select1(.clk(clk), .rst(rst), .ea(ea), .ea_int(ea_int), .op1_i(op1_i),
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.op2_i(op2_i), .op3_i(op3_i), .op1_x(op1), .op2_x(op2), .op3_x(op3),
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.op2_i(op2_i), .op3_i(op3_i), .op1_x(op1), .op2_x(op2), .op3_x(op3),
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.op1_out(op1_n), .op2_out(op2_n), .op2_direct(op2_dr), .op3_out(op3_n),
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.op1_out(op1_n), .op2_out(op2_n), .op2_direct(op2_dr), .op3_out(op3_n),
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.intr(intr), .int_v(int_src), .rd(rd), .ack(ack), .istb(istb), .istb_o(istb_o),
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.intr(intr), .int_v(int_src), .rd(rd), .ack(ack), .istb(istb),
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.iack_i(iack_i));
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.istb_o(istb_o), .iack_i(iack_i), .nop(nop));
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//
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//
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// serial interface
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// serial interface
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oc8051_uart oc8051_uatr1 (.clk(clk), .rst(rst), .bit_in(desCy), .rd_addr(rd_addr),
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oc8051_uart oc8051_uatr1 (.clk(clk), .rst(rst), .bit_in(desCy), .rd_addr(rd_addr),
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.data_in(des1), .wr(wr_r), .wr_bit(bit_addr_r), .wr_addr(wr_addr),
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.data_in(des1), .wr(wr_r), .wr_bit(bit_addr_r), .wr_addr(wr_addr),
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