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module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,
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module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,
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rxd, txd, int, t1_ow);
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rxd, txd, intr, t1_ow);
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input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;
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input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;
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input [7:0] rd_addr, data_in, wr_addr;
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input [7:0] rd_addr, data_in, wr_addr;
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output txd, int, bit_out;
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output txd, intr, bit_out;
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output [7:0] data_out;
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output [7:0] data_out;
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reg txd, bit_out;
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reg txd, bit_out;
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reg [7:0] data_out;
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reg [7:0] data_out;
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//
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//
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// sam_cnt sample counter
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// sam_cnt sample counter
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reg [2:0] sam_cnt, sample;
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reg [2:0] sam_cnt, sample;
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assign int = scon[1] | scon [0];
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assign intr = scon[1] | scon [0];
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//
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//
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//serial port control register
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//serial port control register
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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end
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end
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end
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end
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//
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//
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//serial port buffer (receive)
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//
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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begin
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sbuf_rxd <= #1 `OC8051_RST_SBUF;
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end
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end
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//
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//serial port buffer (transmit)
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//serial port buffer (transmit)
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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sbuf_txd <= #1 `OC8051_RST_SBUF;
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sbuf_txd <= #1 `OC8051_RST_SBUF;
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tr_start <= 1'b0;
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tr_start <= #1 1'b0;
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end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
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end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
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sbuf_txd <= #1 data_in;
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sbuf_txd <= #1 data_in;
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tr_start <= #1 1'b1;
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tr_start <= #1 1'b1;
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end else
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end else
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tr_start <= #1 1'b0;
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tr_start <= #1 1'b0;
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//
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//
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end else if (trans)
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end else if (trans)
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begin
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begin
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case (scon[7:6])
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case (scon[7:6])
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2'b00: begin //mode 0
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2'b00: begin //mode 0
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if (tr_count==9'd8)
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if (tr_count==4'd8)
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begin
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begin
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trans <= #1 1'b0;
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trans <= #1 1'b0;
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txd <= #1 1'b1;
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txd <= #1 1'b1;
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end else begin
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end else begin
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txd <= #1 sbuf_txd[tr_count];
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txd <= #1 sbuf_txd[tr_count];
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tr_count <= #1 tr_count +1'b1;
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tr_count <= #1 tr_count + 4'b1;
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end
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end
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end
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end
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2'b01: begin // mode 1
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2'b01: begin // mode 1
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if ((t1_ow) & !(t1_ow_buf))
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if ((t1_ow) & !(t1_ow_buf))
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begin
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begin
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4'd8: txd <= #1 1'b1; // stop bit
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4'd8: txd <= #1 1'b1; // stop bit
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4'd9: trans <= #1 1'b0;
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4'd9: trans <= #1 1'b0;
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4'b1111: txd <= #1 1'b0; //start bit
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4'b1111: txd <= #1 1'b0; //start bit
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default: txd <= #1 sbuf_txd[tr_count];
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default: txd <= #1 sbuf_txd[tr_count];
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endcase
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endcase
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tr_count <= #1 tr_count +1'b1;
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tr_count <= #1 tr_count + 4'b1;
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smod_cnt_t <= #1 1'b0;
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smod_cnt_t <= #1 1'b0;
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end else smod_cnt_t <= #1 1'b1;
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end else smod_cnt_t <= #1 1'b1;
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end
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end
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end
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end
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2'b10: begin // mode 2
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2'b10: begin // mode 2
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default: begin
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default: begin
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txd <= #1 sbuf_txd[tr_count];
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txd <= #1 sbuf_txd[tr_count];
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end
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end
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endcase
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endcase
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tr_count <= #1 tr_count+1'b1;
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tr_count <= #1 tr_count+1'b1;
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mode2_count <= #1 4'd0;
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mode2_count <= #1 3'd0;
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end else begin
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end else begin
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mode2_count <= #1 mode2_count + 1'b1;
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mode2_count <= #1 mode2_count + 3'b1;
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end
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end
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end
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end
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default: begin // mode 3
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default: begin // mode 3
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if ((t1_ow) & !(t1_ow_buf))
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if ((t1_ow) & !(t1_ow_buf))
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begin
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begin
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end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
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end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
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pcon <= #1 data_in;
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pcon <= #1 data_in;
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end
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end
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//
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//
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// receive
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//serial port buffer (receive)
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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sample <= #1 3'b000;
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sample <= #1 3'b000;
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sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
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sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
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end else begin
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end else begin
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sbuf_rxd_tmp[re_count+1] <= #1 rxd;
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sbuf_rxd_tmp[re_count+1] <= #1 rxd;
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r_int <= #1 1'b0;
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r_int <= #1 1'b0;
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end
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end
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re_count <= #1 re_count + 1'b1;
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re_count <= #1 re_count + 4'b1;
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end
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end
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2'b01: begin // mode 1
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2'b01: begin // mode 1
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if ((t1_ow) & !(t1_ow_buf))
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if ((t1_ow) & !(t1_ow_buf))
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begin
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begin
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if ((pcon[7]) | (smod_cnt_r))
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if ((pcon[7]) | (smod_cnt_r))
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begin
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begin
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sam_cnt <= #1 3'b000;
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sam_cnt <= #1 3'b000;
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r_int <= #1 1'b0;
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r_int <= #1 1'b0;
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re_count <= #1 re_count +1'b1;
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re_count <= #1 re_count + 4'b1;
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smod_cnt_r <= #1 1'b0;
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smod_cnt_r <= #1 1'b0;
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end else smod_cnt_r <= #1 1'b1;
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end else smod_cnt_r <= #1 1'b1;
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end else begin
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end else begin
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if (sam_cnt==3'b011) begin
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if (sam_cnt==3'b011) begin
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if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
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if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
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end else begin
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end else begin
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sam_cnt <= #1 3'b001;
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sam_cnt <= #1 3'b001;
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sample[0] <= #1 rxd;
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sample[0] <= #1 rxd;
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r_int <= #1 1'b0;
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r_int <= #1 1'b0;
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end
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end
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re_count <= #1 re_count + 1'b1;
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re_count <= #1 re_count + 4'b1;
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end else begin
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end else begin
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r_int <= #1 1'b0;
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r_int <= #1 1'b0;
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if (sam_cnt==3'b011) begin
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if (sam_cnt==3'b011) begin
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if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
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if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
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end else begin
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end else begin
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sam_cnt <= #1 3'b000;
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sam_cnt <= #1 3'b000;
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r_int <= #1 1'b0;
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r_int <= #1 1'b0;
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end
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end
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re_count <= #1 re_count +1'b1;
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re_count <= #1 re_count + 4'b1;
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smod_cnt_r <= #1 1'b0;
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smod_cnt_r <= #1 1'b0;
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end else smod_cnt_r <= #1 1'b1;
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end else smod_cnt_r <= #1 1'b1;
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end else begin
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end else begin
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r_int <= #1 1'b0;
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r_int <= #1 1'b0;
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if (sam_cnt==3'b011)
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if (sam_cnt==3'b011)
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Line 343... |
end
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end
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//
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//
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//
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//
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//
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//
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always @(posedge clk)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) |
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if (rst) data_out <= #1 8'h0;
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else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) |
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(wr_addr==`OC8051_SFR_SCON))) begin
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(wr_addr==`OC8051_SFR_SCON))) begin
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data_out <= #1 data_in;
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data_out <= #1 data_in;
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end else begin
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end else begin
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case (rd_addr)
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case (rd_addr)
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`OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
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`OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
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Line 359... |
endcase
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endcase
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end
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end
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end
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end
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always @(posedge clk)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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trans_buf <= #1 1'b0;
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receive_buf <= #1 1'b0;
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t1_ow_buf <= #1 1'b0;
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rxd_buf <= #1 1'b0;
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end else begin
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trans_buf <= #1 trans;
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trans_buf <= #1 trans;
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end
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always @(posedge clk)
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begin
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receive_buf <= #1 receive;
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receive_buf <= #1 receive;
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end
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always @(posedge clk)
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begin
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t1_ow_buf <= #1 t1_ow;
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t1_ow_buf <= #1 t1_ow;
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end
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always @(posedge clk)
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begin
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rxd_buf <= #1 rxd;
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rxd_buf <= #1 rxd;
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end
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk)
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begin
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begin
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if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
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if (rst) bit_out <= #1 1'b0;
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else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
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bit_out <= #1 bit_in;
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bit_out <= #1 bit_in;
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end else
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end else
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bit_out <= #1 scon[rd_addr[2:0]];
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bit_out <= #1 scon[rd_addr[2:0]];
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end
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end
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endmodule
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endmodule
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