OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_uart.v] - Diff between revs 4 and 5

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 4 Rev 5
Line 62... Line 62...
    sbuf_txd <= #1 `OC8051_RST_SBUF;
    sbuf_txd <= #1 `OC8051_RST_SBUF;
    tr_start <= #1 1'b0;
    tr_start <= #1 1'b0;
  end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
  end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
    sbuf_txd <= #1 data_in;
    sbuf_txd <= #1 data_in;
    tr_start <= #1 1'b1;
    tr_start <= #1 1'b1;
   end else
  end else tr_start <= #1 1'b0;
    tr_start <= #1 1'b0;
 
end
end
 
 
//
//
// transmit
// transmit
//
//
Line 216... Line 215...
        if (re_count==4'd8) begin
        if (re_count==4'd8) begin
          receive <= #1 1'b0;
          receive <= #1 1'b0;
          r_int <= #1 1'b1;
          r_int <= #1 1'b1;
          sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
          sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
        end else begin
        end else begin
          sbuf_rxd_tmp[re_count+1] <= #1 rxd;
          sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;
          r_int <= #1 1'b0;
          r_int <= #1 1'b0;
        end
        end
        re_count <= #1 re_count + 4'b1;
        re_count <= #1 re_count + 4'd1;
      end
      end
      2'b01: begin // mode 1
      2'b01: begin // mode 1
        if ((t1_ow) & !(t1_ow_buf))
        if ((t1_ow) & !(t1_ow_buf))
        begin
        begin
          if ((pcon[7]) | (smod_cnt_r))
          if ((pcon[7]) | (smod_cnt_r))
          begin
          begin
            sam_cnt <= #1 3'b000;
            sam_cnt <= #1 3'b000;
            r_int <= #1 1'b0;
            r_int <= #1 1'b0;
 
 
            re_count <= #1 re_count + 4'b1;
            re_count <= #1 re_count + 4'd1;
            smod_cnt_r <= #1 1'b0;
            smod_cnt_r <= #1 1'b0;
          end else smod_cnt_r <= #1 1'b1;
          end else smod_cnt_r <= #1 1'b1;
        end else begin
        end else begin
          if (sam_cnt==3'b011) begin
          if (sam_cnt==3'b011) begin
            if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
            if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
            else
            else
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
            if (re_count==4'h9)
            if (re_count == 4'd9)
            begin
            begin
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
              receive <= #1 1'b0;
              receive <= #1 1'b0;
              r_int <= #1 1'b1;
              r_int <= #1 1'b1;
            end else r_int <= #1 1'b0;
            end else r_int <= #1 1'b0;
Line 262... Line 261...
          end else begin
          end else begin
            sam_cnt <= #1 3'b001;
            sam_cnt <= #1 3'b001;
            sample[0] <= #1 rxd;
            sample[0] <= #1 rxd;
            r_int <= #1 1'b0;
            r_int <= #1 1'b0;
          end
          end
    re_count <= #1 re_count + 4'b1;
    re_count <= #1 re_count + 4'd1;
        end else begin
        end else begin
          r_int <= #1 1'b0;
          r_int <= #1 1'b0;
 
 
          if (sam_cnt==3'b011) begin
          if (sam_cnt==3'b011) begin
            if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
            if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
Line 293... Line 292...
            end else begin
            end else begin
              sam_cnt <= #1 3'b000;
              sam_cnt <= #1 3'b000;
              r_int <= #1 1'b0;
              r_int <= #1 1'b0;
            end
            end
 
 
            re_count <= #1 re_count + 4'b1;
            re_count <= #1 re_count + 4'd1;
            smod_cnt_r <= #1 1'b0;
            smod_cnt_r <= #1 1'b0;
          end else smod_cnt_r <= #1 1'b1;
          end else smod_cnt_r <= #1 1'b1;
        end else begin
        end else begin
          r_int <= #1 1'b0;
          r_int <= #1 1'b0;
          if (sam_cnt==3'b011)
          if (sam_cnt==3'b011)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.