| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2003/04/02 15:08:59 simont
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// rename signals
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//
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// Revision 1.8 2003/01/13 14:35:25 simont
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// Revision 1.8 2003/01/13 14:35:25 simont
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// remove wb_bus_mon
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// remove wb_bus_mon
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//
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//
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// Revision 1.7 2002/10/28 16:43:12 simont
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// Revision 1.7 2002/10/28 16:43:12 simont
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// add module oc8051_wb_iinterface
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// add module oc8051_wb_iinterface
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| Line 130... |
Line 133... |
.txd(rxd), .ow(p3_out[1]), .intr(int_uart), .stb(stb_o), .ack(ack_uart));
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.txd(rxd), .ow(p3_out[1]), .intr(int_uart), .stb(stb_o), .ack(ack_uart));
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//
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//
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// exteranl program rom
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// exteranl program rom
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//
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//
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// cache
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//
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//
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wire istb_i, icyc_i, iack_o;
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wire [15:0] iadr_i;
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wire [31:0] idat_o;
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`ifdef OC8051_CACHE
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oc8051_icache oc8051_icache1(.rst(rst), .clk(clk),
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// oc8051
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.adr_i(iadr_o), .dat_o(idat_i), .stb_i(istb_o), .ack_o(iack_i),
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.cyc_i(icyc_o),
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// external rom
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.dat_i(idat_o), .stb_o(istb_i), .adr_o(iadr_i), .ack_i(iack_o),
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.cyc_o(icyc_i));
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_i), .data(idat_o),
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.stb_i(istb_i), .cyc_i(icyc_i), .ack_o(iack_o));
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defparam oc8051_icache1.ADR_WIDTH = 7; // cache address wihth
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defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)
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defparam oc8051_icache1.BL_NUM = 15; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
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defparam oc8051_icache1.CACHE_RAM = 128; // cache ram x 32 (2^ADR_WIDTH)
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//
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// no cache
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//
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`else
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oc8051_wb_iinterface oc8051_wb_iinterface(.rst(rst), .clk(clk),
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// oc8051
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.adr_i(iadr_o), .dat_o(idat_i), .stb_i(istb_o), .ack_o(iack_i),
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.cyc_i(icyc_o),
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// external rom
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.dat_i(idat_o), .stb_o(istb_i), .adr_o(iadr_i), .ack_i(iack_o),
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.cyc_o(icyc_i));
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_i), .data(idat_o),
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_o), .data(idat_i),
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.stb_i(istb_i), .cyc_i(icyc_i), .ack_o(iack_o));
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.stb_i(istb_o), .cyc_i(icyc_o), .ack_o(iack_i));
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`endif
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//
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//
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//
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//
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//
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//
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defparam oc8051_xrom1.DELAY = 5;
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defparam oc8051_xrom1.DELAY = 5;
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| Line 215... |
Line 178... |
p1_in = 8'h00;
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p1_in = 8'h00;
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p2_in = 8'h00;
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p2_in = 8'h00;
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#220
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#220
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rst = 1'b0;
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rst = 1'b0;
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#7000000
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#40000000
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$fclose(log_file);
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$fclose(log_file);
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$display("time ",$time, "\n faulire: end of time\n \n");
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$display("time ",$time, "\n faulire: end of time\n \n");
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$finish;
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$finish;
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end
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end
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initial
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initial
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begin
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begin
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clk = 0;
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clk = 0;
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forever #70 clk <= ~clk;
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forever #30 clk <= ~clk;
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end
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end
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initial
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initial
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