| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2003/04/03 19:20:55 simont
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// Remove instruction cache and wb_interface
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//
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// Revision 1.9 2003/04/02 15:08:59 simont
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// Revision 1.9 2003/04/02 15:08:59 simont
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// rename signals
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// rename signals
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//
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//
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// Revision 1.8 2003/01/13 14:35:25 simont
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// Revision 1.8 2003/01/13 14:35:25 simont
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// remove wb_bus_mon
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// remove wb_bus_mon
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| Line 107... |
Line 110... |
.wbd_ack_i(ack_i), .wbd_stb_o(stb_o), .wbd_cyc_o(cyc_o),
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.wbd_ack_i(ack_i), .wbd_stb_o(stb_o), .wbd_cyc_o(cyc_o),
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.wbi_adr_o(iadr_o), .wbi_stb_o(istb_o), .wbi_ack_i(iack_i),
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.wbi_adr_o(iadr_o), .wbi_stb_o(istb_o), .wbi_ack_i(iack_i),
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.wbi_cyc_o(icyc_o), .wbi_dat_i(idat_i), .wbi_err_i(wbi_err_i),
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.wbi_cyc_o(icyc_o), .wbi_dat_i(idat_i), .wbi_err_i(wbi_err_i),
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.p0_i(p0_in), .p1_i(p1_in), .p2_i(p2_in), .p3_i(p3_in),
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`ifdef OC8051_PORTS
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.p0_o(p0_out), .p1_o(p1_out), .p2_o(p2_out), .p3_o(p3_out),
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`ifdef OC8051_PORT0
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.p0_i(p0_in),
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.p0_o(p0_out),
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`endif
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`ifdef OC8051_PORT1
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.p1_i(p1_in),
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.p1_o(p1_out),
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`endif
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`ifdef OC8051_PORT2
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.p2_i(p2_in),
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.p2_o(p2_out),
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`endif
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`ifdef OC8051_PORT3
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.p3_i(p3_in),
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.p3_o(p3_out),
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`endif
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`endif
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.ea_in(ea[0]),
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`ifdef OC8051_UART
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.rxd_i(rxd), .txd_o(txd),
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.rxd_i(rxd), .txd_o(txd),
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.t0_i(t0), .t1_i(t1), .t2_i(t2), .t2ex_i(t2ex));
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`endif
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`ifdef OC8051_TC01
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.t0_i(t0), .t1_i(t1),
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`endif
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`ifdef OC8051_TC2
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.t2_i(t2), .t2ex_i(t2ex),
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`endif
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.ea_in(ea[0]));
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//
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//
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// external data ram
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// external data ram
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//
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//
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