| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.12 2003/04/16 09:55:56 simont
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// add support for external rom from xilinx ramb4
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//
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// Revision 1.11 2003/04/10 12:45:06 simont
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// Revision 1.11 2003/04/10 12:45:06 simont
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// defines for pherypherals added
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// defines for pherypherals added
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//
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//
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// Revision 1.10 2003/04/03 19:20:55 simont
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// Revision 1.10 2003/04/03 19:20:55 simont
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// Remove instruction cache and wb_interface
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// Remove instruction cache and wb_interface
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| Line 77... |
Line 80... |
`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_tb;
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module oc8051_tb;
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//parameter FREQ = 20000; // frequency in kHz
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parameter FREQ = 12000; // frequency in kHz
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parameter DELAY = 500000/FREQ;
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reg rst, clk;
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reg rst, clk;
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reg [7:0] p0_in, p1_in, p2_in;
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reg [7:0] p0_in, p1_in, p2_in;
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wire [15:0] ext_addr, iadr_o;
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wire [15:0] ext_addr, iadr_o;
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wire write, write_xram, write_uart, txd, rxd, int_uart, int0, int1, t0, t1, bit_out, stb_o, ack_i;
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wire write, write_xram, write_uart, txd, rxd, int_uart, int0, int1, t0, t1, bit_out, stb_o, ack_i;
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wire ack_xram, ack_uart, cyc_o, iack_i, istb_o, icyc_o, t2, t2ex;
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wire ack_xram, ack_uart, cyc_o, iack_i, istb_o, icyc_o, t2, t2ex;
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| Line 164... |
Line 173... |
oc8051_xram oc8051_xram1 (.clk(clk), .rst(rst), .wr(write_xram), .addr(ext_addr), .data_in(data_out), .data_out(data_out_xram), .ack(ack_xram), .stb(stb_o));
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oc8051_xram oc8051_xram1 (.clk(clk), .rst(rst), .wr(write_xram), .addr(ext_addr), .data_in(data_out), .data_out(data_out_xram), .ack(ack_xram), .stb(stb_o));
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defparam oc8051_xram1.DELAY = 2;
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defparam oc8051_xram1.DELAY = 2;
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`ifdef OC8051_SERIAL
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//
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// test programs with serial interface
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//
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oc8051_serial oc8051_serial1(.clk(clk), .rst(rst), .rxd(txd), .txd(rxd));
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defparam oc8051_serial1.FREQ = FREQ;
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//defparam oc8051_serial1.BRATE = 9.6;
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defparam oc8051_serial1.BRATE = 4.8;
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`else
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//
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//
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// external uart
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// external uart
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//
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//
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oc8051_uart_test oc8051_uart_test1(.clk(clk), .rst(rst), .addr(ext_addr[7:0]), .wr(write_uart),
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oc8051_uart_test oc8051_uart_test1(.clk(clk), .rst(rst), .addr(ext_addr[7:0]), .wr(write_uart),
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.wr_bit(p3_out[0]), .data_in(data_out), .data_out(data_out_uart), .bit_out(bit_out), .rxd(txd),
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.wr_bit(p3_out[0]), .data_in(data_out), .data_out(data_out_uart), .bit_out(bit_out), .rxd(txd),
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.txd(rxd), .ow(p3_out[1]), .intr(int_uart), .stb(stb_o), .ack(ack_uart));
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.txd(rxd), .ow(p3_out[1]), .intr(int_uart), .stb(stb_o), .ack(ack_uart));
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`endif
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`ifdef OC8051_XILINX_RAMB
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`ifdef OC8051_XILINX_RAMB
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`include "oc8051_rom_values.v"
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`include "oc8051_rom_values.v"
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| Line 241... |
Line 266... |
`else
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`else
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_o), .data(idat_i),
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_o), .data(idat_i),
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.stb_i(istb_o), .cyc_i(icyc_o), .ack_o(iack_i));
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.stb_i(istb_o), .cyc_i(icyc_o), .ack_o(iack_i));
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defparam oc8051_xrom1.DELAY = 5;
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defparam oc8051_xrom1.DELAY = 0;
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`endif
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`endif
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//
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//
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//
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//
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//
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//
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//
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// test wb interface
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//
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reg [31:0] log_file;
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initial
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begin
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log_file = $fopen("log_file");
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$fdisplay(log_file, "file open");
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end
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assign write_xram = p3_out[7] & write;
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assign write_xram = p3_out[7] & write;
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assign write_uart = !p3_out[7] & write;
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assign write_uart = !p3_out[7] & write;
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assign data_in = p3_out[7] ? data_out_xram : data_out_uart;
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assign data_in = p3_out[7] ? data_out_xram : data_out_uart;
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assign ack_i = p3_out[7] ? ack_xram : ack_uart;
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assign ack_i = p3_out[7] ? ack_xram : ack_uart;
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assign p3_in = {6'h0, bit_out, int_uart};
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assign p3_in = {6'h0, bit_out, int_uart};
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| Line 284... |
Line 296... |
p1_in = 8'h00;
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p1_in = 8'h00;
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p2_in = 8'h00;
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p2_in = 8'h00;
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#220
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#220
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rst = 1'b0;
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rst = 1'b0;
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#40000000
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#80000000
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$fclose(log_file);
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$display("time ",$time, "\n faulire: end of time\n \n");
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$display("time ",$time, "\n faulire: end of time\n \n");
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$finish;
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$finish;
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end
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end
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initial
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initial
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begin
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begin
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clk = 0;
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clk = 0;
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forever #30 clk <= ~clk;
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forever #DELAY clk <= ~clk;
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end
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end
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initial
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initial
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| Line 317... |
Line 328... |
$display("time ",$time, " faulire: mismatch on ports in step %d", num);
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$display("time ",$time, " faulire: mismatch on ports in step %d", num);
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$display(" p0_out %h", p0_out, " p1_out %h", p1_out, " p2_out %h", p2_out);
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$display(" p0_out %h", p0_out, " p1_out %h", p1_out, " p2_out %h", p2_out);
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$display(" testvecp %h", buff[num]);
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$display(" testvecp %h", buff[num]);
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$display(" p_out %h%h%h", p0_out, p1_out, p2_out);
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$display(" p_out %h%h%h", p0_out, p1_out, p2_out);
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#22
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#22
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$fclose(log_file);
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$finish;
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$finish;
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end
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end
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else begin
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else begin
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$display("time ",$time, " step %d", num, ": pass");
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$display("time ",$time, " step %d", num, ": pass");
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num = num+1;
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num = num+1;
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if (buff[num]===24'hxxxxxx)
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if (buff[num]===24'hxxxxxx)
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begin
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begin
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$display("");
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$display("");
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$display(" Done!");
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$display(" Done!");
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$fclose(log_file);
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$finish;
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$finish;
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end
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end
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end
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end
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end
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end
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