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Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2003/04/02 11:38:40 simont
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// initial inport
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//
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// Revision 1.4 2002/09/30 17:34:01 simont
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// Revision 1.4 2002/09/30 17:34:01 simont
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// prepared header
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// prepared header
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//
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//
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//
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//
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| Line 75... |
Line 78... |
input clk, rst, wr, wr_bit, rxd, ow, stb;
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input clk, rst, wr, wr_bit, rxd, ow, stb;
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input [7:0] addr, data_in;
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input [7:0] addr, data_in;
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output txd, intr, bit_out, ack;
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output txd, intr, bit_out, ack;
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output [7:0] data_out;
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output [7:0] data_out;
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reg [7:0] data_out;
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wire syn;
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wire syn;
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reg wr_r, ack;
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reg wr_r, ack;
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reg [7:0] addr_r, data_in_r;
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reg [7:0] addr_r, data_in_r;
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wire tclk, rclk, brate2;
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oc8051_uart oc8051_uart_test(.rst(rst), .clk(clk), .bit_in(data_in[0]), .rd_addr(addr), .data_in(data_in_r),
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assign tclk = 0;
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.wr(wr_r), .wr_bit(wr_bit), .wr_addr(addr_r), .data_out(data_out), .bit_out(bit_out),
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assign rclk = 0;
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.rxd(rxd), .txd(txd), .intr(intr), .t1_ow(ow));
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assign brate2 = 0;
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reg pres_ow;
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reg [3:0] prescaler;
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wire [7:0] scon, pcon, sbuf;
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oc8051_uart oc8051_uart_test(.rst(rst), .clk(clk), .bit_in(data_in[0]),
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.data_in(data_in_r), .wr(wr_r), .wr_bit(wr_bit), .wr_addr(addr_r),
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.rxd(rxd), .txd(txd), .intr(intr), .t1_ow(ow),
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.rclk(rclk), .tclk(tclk),
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.pres_ow(pres_ow), .brate2(brate2),
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.scon(scon), .pcon(pcon), .sbuf(sbuf));
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (ack) ack <= #1 1'b0;
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if (ack) ack <= #1 1'b0;
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else
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else
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| Line 100... |
Line 116... |
wr_r <= #1 wr;
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wr_r <= #1 wr;
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addr_r <= #1 addr;
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addr_r <= #1 addr;
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data_in_r <= #1 data_in;
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data_in_r <= #1 data_in;
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end
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end
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always @(posedge clk or posedge rst)
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begin
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if (rst) begin
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prescaler <= #1 4'h5;
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pres_ow <= #1 1'b0;
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end else if (prescaler==4'b1011) begin
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prescaler <= #1 4'h0;
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pres_ow <= #1 1'b1;
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end else begin
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prescaler <= #1 prescaler + 4'h1;
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pres_ow <= #1 1'b0;
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end
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end
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always @(addr or
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// serial interface
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scon or pcon or sbuf)
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begin
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case (addr)
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`OC8051_SFR_SCON: data_out = scon;
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`OC8051_SFR_SBUF: data_out = sbuf;
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`OC8051_SFR_PCON: data_out = pcon;
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default: data_out = 8'h00;
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endcase
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end
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assign bit_out = scon[addr[2:0]];
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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