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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_acc.v] - Diff between revs 118 and 153
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| Rev 118 |
Rev 153 |
| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.12 2003/04/09 16:24:03 simont
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// change wr_sft to 2 bit wire.
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//
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// Revision 1.11 2003/04/09 15:49:42 simont
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// Revision 1.11 2003/04/09 15:49:42 simont
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// Register oc8051_sfr dato output, add signal wait_data.
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// Register oc8051_sfr dato output, add signal wait_data.
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//
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//
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// Revision 1.10 2003/04/07 14:58:02 simont
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// Revision 1.10 2003/04/07 14:58:02 simont
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// change sfr's interface.
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// change sfr's interface.
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data_out <= #1 `OC8051_RST_ACC;
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data_out <= #1 `OC8051_RST_ACC;
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else
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else
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data_out <= #1 acc;
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data_out <= #1 acc;
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end
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end
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`ifdef OC8051_SIMULATION
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always @(data_out)
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if (data_out===8'hxx) begin
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$display("time ",$time, " faulire: invalid write to ACC (oc8051_acc)");
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#22
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$finish;
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end
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`endif
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endmodule
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endmodule
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