| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.13 2003/06/03 17:16:16 simont
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// `ifdef added.
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//
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// Revision 1.12 2003/04/09 16:24:03 simont
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// Revision 1.12 2003/04/09 16:24:03 simont
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// change wr_sft to 2 bit wire.
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// change wr_sft to 2 bit wire.
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//
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//
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// Revision 1.11 2003/04/09 15:49:42 simont
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// Revision 1.11 2003/04/09 15:49:42 simont
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// Register oc8051_sfr dato output, add signal wait_data.
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// Register oc8051_sfr dato output, add signal wait_data.
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| Line 103... |
Line 106... |
if (wr2_acc)
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if (wr2_acc)
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acc = data2_in;
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acc = data2_in;
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else if (wr_acc)
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else if (wr_acc)
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acc = data_in;
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acc = data_in;
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else if (wr_bit_acc)
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else if (wr_bit_acc)
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case (wr_addr[2:0])
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case (wr_addr[2:0]) /* synopsys full_case parallel_case */
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3'b000: acc = {data_out[7:1], bit_in};
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3'b000: acc = {data_out[7:1], bit_in};
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3'b001: acc = {data_out[7:2], bit_in, data_out[0]};
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3'b001: acc = {data_out[7:2], bit_in, data_out[0]};
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3'b010: acc = {data_out[7:3], bit_in, data_out[1:0]};
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3'b010: acc = {data_out[7:3], bit_in, data_out[1:0]};
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3'b011: acc = {data_out[7:4], bit_in, data_out[2:0]};
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3'b011: acc = {data_out[7:4], bit_in, data_out[2:0]};
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3'b100: acc = {data_out[7:5], bit_in, data_out[3:0]};
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3'b100: acc = {data_out[7:5], bit_in, data_out[3:0]};
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3'b101: acc = {data_out[7:6], bit_in, data_out[4:0]};
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3'b101: acc = {data_out[7:6], bit_in, data_out[4:0]};
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3'b110: acc = {data_out[7], bit_in, data_out[5:0]};
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3'b110: acc = {data_out[7], bit_in, data_out[5:0]};
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default: acc = {bit_in, data_out[6:0]};
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3'b111: acc = {bit_in, data_out[6:0]};
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endcase
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endcase
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else
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else
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acc = data_out;
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acc = data_out;
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end
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end
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