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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/09/30 17:33:59 simont
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// prepared header
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_acc (clk, rst, bit_in, data_in, data2_in, wr, wr_bit, wad2, wr_addr, rd_addr,
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module oc8051_acc (clk, rst, bit_in, data_in, data2_in, wr, wr_bit, wad2, wr_addr, rd_addr,
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data_out, bit_out, p, stb_o, we_o, ack_i, xdata);
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data_out, bit_out, p, rd_x, xdata);
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// clk (in) clock
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// clk (in) clock
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// rst (in) reset
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// rst (in) reset
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// bit_in (in) bit input - used in case of writing bits to acc (bit adddressable memory space - alu carry) [oc8051_alu.desCy]
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// bit_in (in) bit input - used in case of writing bits to acc (bit adddressable memory space - alu carry) [oc8051_alu.desCy]
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// data_in (in) data input - used to write to acc (from alu destiantion 1) [oc8051_alu.des1]
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// data_in (in) data input - used to write to acc (from alu destiantion 1) [oc8051_alu.des1]
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// data2_in (in) data 2 input - write to acc, from alu detination 2 - instuctions mul and div [oc8051_alu.des2]
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// data2_in (in) data 2 input - write to acc, from alu detination 2 - instuctions mul and div [oc8051_alu.des2]
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// wr_bit (in) write bit addresable - actine high [oc8051_decoder.bit_addr -r]
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// wr_bit (in) write bit addresable - actine high [oc8051_decoder.bit_addr -r]
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// wad2 (in) write data 2 [oc8051_decoder.wad2 -r]
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// wad2 (in) write data 2 [oc8051_decoder.wad2 -r]
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// wr_addr (in) write address (if is addres of acc and white high must be written to acc) [oc8051_ram_wr_sel.out]
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// wr_addr (in) write address (if is addres of acc and white high must be written to acc) [oc8051_ram_wr_sel.out]
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// data_out (out) data output [oc8051_alu_src1_sel.acc oc8051_alu_src2_sel.acc oc8051_comp.acc oc8051_ram_sel.acc]
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// data_out (out) data output [oc8051_alu_src1_sel.acc oc8051_alu_src2_sel.acc oc8051_comp.acc oc8051_ram_sel.acc]
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// p (out) parity [oc8051_psw.p]
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// p (out) parity [oc8051_psw.p]
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// stb_o (in) strobe
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// rd_x (in) read external
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// we_o (in) write to external ram
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// ack_i (in) acknowlage from external ram
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// xdata (in) external data input
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// xdata (in) external data input
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//
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//
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input clk, rst, wr, wr_bit, wad2, bit_in, stb_o, we_o, ack_i;
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input clk, rst, wr, wr_bit, wad2, bit_in, rd_x;
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input [2:0] rd_addr;
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input [2:0] rd_addr;
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input [7:0] wr_addr, data_in, data2_in, xdata;
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input [7:0] wr_addr, data_in, data2_in, xdata;
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output p, bit_out;
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output p, bit_out;
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output [7:0] data_out;
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output [7:0] data_out;
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//must check if write high and correct address
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//must check if write high and correct address
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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data_out <= #1 `OC8051_RST_ACC;
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data_out <= #1 `OC8051_RST_ACC;
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else if (stb_o && !we_o && ack_i)
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else if (rd_x)
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data_out <= #1 xdata;
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data_out <= #1 xdata;
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else if (wad2)
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else if (wad2)
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data_out <= #1 data2_in;
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data_out <= #1 data2_in;
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else if (wr) begin
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else if (wr) begin
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if (!wr_bit) begin
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if (!wr_bit) begin
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