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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_alu.v] - Diff between revs 152 and 171

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Rev 152 Rev 171
Line 44... Line 44...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.16  2003/06/03 17:15:06  simont
 
// sub_result output added.
 
//
// Revision 1.15  2003/05/07 12:31:53  simont
// Revision 1.15  2003/05/07 12:31:53  simont
// add wire sub_result, conect it to des_acc and des1.
// add wire sub_result, conect it to des_acc and des1.
//
//
// Revision 1.14  2003/05/05 15:46:36  simont
// Revision 1.14  2003/05/05 15:46:36  simont
// add aditional alu destination to solve critical path.
// add aditional alu destination to solve critical path.
Line 134... Line 137...
reg enable_div;
reg enable_div;
 
 
//
//
//da
//da
//
//
reg da_tmp;
reg da_tmp, da_tmp1;
//reg [8:0] da1;
//reg [8:0] da1;
 
 
//
//
// inc
// inc
//
//
Line 242... Line 245...
    `OC8051_ALU_DA: begin
    `OC8051_ALU_DA: begin
 
 
      if (srcAc==1'b1 | src1[3:0]>4'b1001) {da_tmp, des_acc[3:0]} = {1'b0, src1[3:0]}+ 5'b00110;
      if (srcAc==1'b1 | src1[3:0]>4'b1001) {da_tmp, des_acc[3:0]} = {1'b0, src1[3:0]}+ 5'b00110;
      else {da_tmp, des_acc[3:0]} = {1'b0, src1[3:0]};
      else {da_tmp, des_acc[3:0]} = {1'b0, src1[3:0]};
 
 
      if (srcCy==1'b1 | src1[7:4]>4'b1001)
      if (srcCy | da_tmp | src1[7:4]>4'b1001)
        {desCy, des_acc[7:4]} = {srcCy, src1[7:4]}+ 5'b00110 + {4'b0, da_tmp};
        {da_tmp1, des_acc[7:4]} = {srcCy, src1[7:4]}+ 5'b00110 + {4'b0, da_tmp};
      else {desCy, des_acc[7:4]} = {srcCy, src1[7:4]} + {4'b0, da_tmp};
      else {da_tmp1, des_acc[7:4]} = {srcCy, src1[7:4]} + {4'b0, da_tmp};
 
 
 
      desCy = da_tmp | da_tmp1;
      des1 = src1;
      des1 = src1;
 
 
      des2 = 8'h00;
      des2 = 8'h00;
      desAc = 1'b0;
      desAc = 1'b0;
      desOv = 1'b0;
      desOv = 1'b0;
      enable_mul = 1'b0;
      enable_mul = 1'b0;
      enable_div = 1'b0;
      enable_div = 1'b0;

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