URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_alu_src_sel.v] - Diff between revs 81 and 141

Rev 81	Rev 141
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2003/01/13 14:13:12 simont`
	`// initial import`
	`//`
`//`	`//`
`//`	`//`

`// synopsys translate_off`	`// synopsys translate_off`
`include "oc8051_timescale.v"	`include "oc8051_timescale.v"
Line 61...	Line 64...

`src1, src2, src3);`	`src1, src2, src3);`


`input clk, rst, rd, sel3;`	`input clk, rst, rd, sel3;`
`input [2:0] sel1, sel2;`	`input [1:0] sel2;`
	`input [2:0] sel1;`
`input [7:0] acc, ram;`	`input [7:0] acc, ram;`
`input [15:0] dptr;`	`input [15:0] dptr;`
`input [15:0] pc;`	`input [15:0] pc;`


Line 100...	Line 104...
`///////`	`///////`
`//`	`//`
`// src2`	`// src2`
`//`	`//`
`///////`	`///////`
`always @(sel2 or op2_r or pc_r or acc or ram or op1_r or pc)`	`always @(sel2 or op2_r or acc or ram or op1_r or pc)`
`begin`	`begin`
`case (sel2)`	`case (sel2)`
`OC8051_AS2_ACC: src2= acc;	`OC8051_AS2_ACC: src2= acc;
`OC8051_AS2_ZERO: src2= 8'h00;	`OC8051_AS2_ZERO: src2= 8'h00;
`OC8051_AS2_RAM: src2= ram;	`OC8051_AS2_RAM: src2= ram;
`OC8051_AS2_OP2: src2= op2_r;	`OC8051_AS2_OP2: src2= op2_r;
`OC8051_AS2_PCL: src2= pc_r[7:0];
`default: src2= 8'h00;`	`default: src2= 8'h00;`
`endcase`	`endcase`
`end`	`end`

`///////`	`///////`