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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_b_register.v] - Diff between revs 5 and 22
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| Rev 5 |
Rev 22 |
| Line 93... |
Line 93... |
end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) bit_out <= #1 1'b0;
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if (rst) bit_out <= #1 1'b0;
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else bit_out <= #1 data_out[rd_addr];
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else if ((rd_addr==wr_addr[2:0]) & wr & wr_bit) begin
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bit_out <= #1 bit_in;
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end else if ((wr_addr[7:5]==`OC8051_SFR_B) & wr & !wr_bit) begin
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bit_out <= #1 data_in[rd_addr];
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end else bit_out <= #1 data_out[rd_addr];
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end
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end
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endmodule
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endmodule
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