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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2003/04/02 11:26:21 simont
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// updating...
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//
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// Revision 1.5 2002/09/30 17:33:59 simont
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// Revision 1.5 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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//
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//
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//
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//
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// synopsys translate_on
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// synopsys translate_on
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_comp (sel, b_in, cy, acc, des, eq);
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module oc8051_comp (sel, b_in, cy, acc, des, /*comp_wait, */eq);
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//
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//
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// sel (in) select whithc sourses to compare (look defines.v) [oc8051_decoder.comp_sel]
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// sel (in) select whithc sourses to compare (look defines.v) [oc8051_decoder.comp_sel]
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// b_in (in) bit in - output from bit addressable memory space [oc8051_ram_sel.bit_out]
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// b_in (in) bit in - output from bit addressable memory space [oc8051_ram_sel.bit_out]
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// cy (in) carry flag [oc8051_psw.data_out[7] ]
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// cy (in) carry flag [oc8051_psw.data_out[7] ]
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// acc (in) accumulator [oc8051_acc.data_out]
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// acc (in) accumulator [oc8051_acc.data_out]
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// eq (out) if (src1 == src2) eq = 1 [oc8051_decoder.eq]
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// eq (out) if (src1 == src2) eq = 1 [oc8051_decoder.eq]
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//
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//
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input [1:0] sel;
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input [1:0] sel;
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input b_in, cy;
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input b_in, cy/*, comp_wait*/;
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input [7:0] acc, des;
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input [7:0] acc, des;
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output eq;
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output eq;
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reg eq;
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reg eq_r;
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assign eq = eq_r;// & comp_wait;
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always @(sel or b_in or cy or acc or des)
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always @(sel or b_in or cy or acc or des)
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begin
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begin
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case (sel)
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case (sel)
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`OC8051_CSS_AZ : eq = (acc == 8'h00);
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`OC8051_CSS_AZ : eq_r = (acc == 8'h00);
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`OC8051_CSS_DES : eq = (des == 8'h00);
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`OC8051_CSS_DES : eq_r = (des == 8'h00);
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`OC8051_CSS_CY : eq = cy;
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`OC8051_CSS_CY : eq_r = cy;
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`OC8051_CSS_BIT : eq = b_in;
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`OC8051_CSS_BIT : eq_r = b_in;
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default: eq = 1'bx;
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default: eq_r = 1'bx;
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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