| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
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// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
|
|
// Revision 1.17 2003/04/25 17:15:51 simont
|
|
// change branch instruction execution (reduse needed clock periods).
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|
//
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// Revision 1.16 2003/04/09 16:24:03 simont
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// Revision 1.16 2003/04/09 16:24:03 simont
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// change wr_sft to 2 bit wire.
|
// change wr_sft to 2 bit wire.
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//
|
//
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// Revision 1.15 2003/04/09 15:49:42 simont
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// Revision 1.15 2003/04/09 15:49:42 simont
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// Register oc8051_sfr dato output, add signal wait_data.
|
// Register oc8051_sfr dato output, add signal wait_data.
|
| Line 1037... |
Line 1040... |
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_SO2;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_BIT;
|
comp_sel = `OC8051_CSS_BIT;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b0;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_JBC : begin
|
`OC8051_JBC : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_BIT;
|
comp_sel = `OC8051_CSS_BIT;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b0;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_JC : begin
|
`OC8051_JC : begin
|
ram_rd_sel = `OC8051_RRS_PSW;
|
ram_rd_sel = `OC8051_RRS_PSW;
|
pc_wr = eq;
|
pc_wr = eq;
|
pc_sel = `OC8051_PIS_SO1;
|
pc_sel = `OC8051_PIS_SO1;
|
comp_sel = `OC8051_CSS_CY;
|
comp_sel = `OC8051_CSS_CY;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_JMP_D : begin
|
`OC8051_JMP_D : begin
|
ram_rd_sel = `OC8051_RRS_DPTR;
|
ram_rd_sel = `OC8051_RRS_DPTR;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
| Line 1074... |
Line 1077... |
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_SO2;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_BIT;
|
comp_sel = `OC8051_CSS_BIT;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b0;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_JNC : begin
|
`OC8051_JNC : begin
|
ram_rd_sel = `OC8051_RRS_PSW;
|
ram_rd_sel = `OC8051_RRS_PSW;
|
pc_wr = !eq;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_SO1;
|
pc_sel = `OC8051_PIS_SO1;
|
comp_sel = `OC8051_CSS_CY;
|
comp_sel = `OC8051_CSS_CY;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_JNZ : begin
|
`OC8051_JNZ : begin
|
ram_rd_sel = `OC8051_RRS_ACC;
|
ram_rd_sel = `OC8051_RRS_ACC;
|
pc_wr = !eq;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_SO1;
|
pc_sel = `OC8051_PIS_SO1;
|
comp_sel = `OC8051_CSS_AZ;
|
comp_sel = `OC8051_CSS_AZ;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_JZ : begin
|
`OC8051_JZ : begin
|
ram_rd_sel = `OC8051_RRS_ACC;
|
ram_rd_sel = `OC8051_RRS_ACC;
|
pc_wr = eq;
|
pc_wr = eq;
|
pc_sel = `OC8051_PIS_SO1;
|
pc_sel = `OC8051_PIS_SO1;
|
comp_sel = `OC8051_CSS_AZ;
|
comp_sel = `OC8051_CSS_AZ;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_LCALL :begin
|
`OC8051_LCALL :begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_Y;
|
pc_wr = `OC8051_PCW_Y;
|
| Line 1390... |
Line 1393... |
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_Y;
|
pc_wr = `OC8051_PCW_Y;
|
pc_sel = `OC8051_PIS_SO1;
|
pc_sel = `OC8051_PIS_SO1;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_SUBB_D : begin
|
`OC8051_SUBB_D : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
| Line 1798... |
Line 1801... |
end
|
end
|
`OC8051_DEC_R : begin
|
`OC8051_DEC_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_DJNZ_R : begin
|
`OC8051_DJNZ_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_INC_R : begin
|
`OC8051_INC_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_R : begin
|
`OC8051_MOV_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
| Line 1976... |
Line 1979... |
end
|
end
|
`OC8051_DEC_I : begin
|
`OC8051_DEC_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_INC_I : begin
|
`OC8051_INC_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_I : begin
|
`OC8051_MOV_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
| Line 2341... |
Line 2344... |
end
|
end
|
`OC8051_DEC_A : begin
|
`OC8051_DEC_A : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_DEC_D : begin
|
`OC8051_DEC_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
| Line 2374... |
Line 2377... |
end
|
end
|
`OC8051_DJNZ_D : begin
|
`OC8051_DJNZ_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_INC_A : begin
|
`OC8051_INC_A : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_INC_D : begin
|
`OC8051_INC_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_INC_DP : begin
|
`OC8051_INC_DP : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
| Line 2416... |
Line 2419... |
src_sel3 <= #1 `OC8051_AS3_DP;
|
src_sel3 <= #1 `OC8051_AS3_DP;
|
wr_sfr <= #1 `OC8051_WRS_DPTR;
|
wr_sfr <= #1 `OC8051_WRS_DPTR;
|
end
|
end
|
`OC8051_JB : begin
|
`OC8051_JB : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_PCL;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_PCS;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_JBC :begin
|
`OC8051_JBC :begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_PCL;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_PCS;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_JC : begin
|
`OC8051_JC : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_PCL;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_PCS;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
| Line 2460... |
Line 2463... |
src_sel3 <= #1 `OC8051_AS3_DP;
|
src_sel3 <= #1 `OC8051_AS3_DP;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_JNB : begin
|
`OC8051_JNB : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_PCL;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_PCS;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_JNC : begin
|
`OC8051_JNC : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_PCL;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_PCS;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_JNZ :begin
|
`OC8051_JNZ :begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_PCL;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_PCS;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_JZ : begin
|
`OC8051_JZ : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_PCL;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_PCS;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
