| Line 87... |
Line 87... |
input clk, rst, eq;
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input clk, rst, eq;
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input [7:0] op_in;
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input [7:0] op_in;
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|
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output wr, reti, write_x, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel,
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output wr, reti, write_x, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel,
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pc_wr, wad2, rmw;
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pc_wr, wad2, rmw;
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output [1:0] ram_rd_sel, src_sel1, src_sel2, psw_set, cy_sel, pc_sel;
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output [1:0] ram_rd_sel, src_sel1, src_sel2, psw_set, cy_sel, pc_sel, comp_sel;
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output [2:0] ram_wr_sel, comp_sel, imm_sel;
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output [2:0] ram_wr_sel, imm_sel;
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output [3:0] alu_op;
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output [3:0] alu_op;
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output rd;
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output rd;
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|
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reg reti, write_x, rmw;
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reg reti, write_x, rmw;
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reg wr, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel, pc_wr, wad2;
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reg wr, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel, pc_wr, wad2;
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| Line 2914... |
Line 2914... |
//
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//
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// in case of instructions that needs more than one clock set state
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// in case of instructions that needs more than one clock set state
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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state <= #1 2'b00;
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state <= #1 2'b01;
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else begin
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else begin
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case (state)
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case (state)
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2'b10: state <= #1 2'b01;
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2'b10: state <= #1 2'b01;
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2'b11: state <= #1 2'b10;
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2'b11: state <= #1 2'b10;
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2'b00:
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2'b00:
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