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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_decoder.v] - Diff between revs 23 and 40

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Line 1... Line 1...
////////////////////////////////////////////////////////////////////// ////                                                              ////
////////////////////////////////////////////////////////////////////// 
 
////                                                              ////
////  8051 core decoder                                           ////
////  8051 core decoder                                           ////
////                                                              ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////                                                              ////
Line 52... Line 53...
 
 
 
 
 
 
module oc8051_decoder (clk, rst, op_in, eq, ram_rd_sel, ram_wr_sel, bit_addr,
module oc8051_decoder (clk, rst, op_in, eq, ram_rd_sel, ram_wr_sel, bit_addr,
wr, src_sel1, src_sel2, src_sel3, alu_op, psw_set, cy_sel, imm_sel, pc_wr,
wr, src_sel1, src_sel2, src_sel3, alu_op, psw_set, cy_sel, imm_sel, pc_wr,
pc_sel, comp_sel, rom_addr_sel, ext_addr_sel, wad2, rd, write_x, reti,
pc_sel, comp_sel, rom_addr_sel, ext_addr_sel, wad2, rd, we_o, reti,
rmw);
rmw, stb_o, ack_i, wr_xaddr);
//
//
// clk          (in)  clock
// clk          (in)  clock
// rst          (in)  reset
// rst          (in)  reset
// op_in        (in)  operation code [oc8051_op_select.op1]
// op_in        (in)  operation code [oc8051_op_select.op1]
// eq           (in)  compare result [oc8051_comp.eq]
// eq           (in)  compare result [oc8051_comp.eq]
Line 77... Line 78...
// pc_wr        (out) pc write [oc8051_pc.wr]
// pc_wr        (out) pc write [oc8051_pc.wr]
// pc_sel       (out) pc select [oc8051_pc.pc_wr_sel]
// pc_sel       (out) pc select [oc8051_pc.pc_wr_sel]
// rom_addr_sel (out) rom address select (alu destination or pc) [oc8051_rom_addr_sel.select]
// rom_addr_sel (out) rom address select (alu destination or pc) [oc8051_rom_addr_sel.select]
// ext_addr_sel (out) external address select (dptr or Ri) [oc8051_ext_addr_sel.select]
// ext_addr_sel (out) external address select (dptr or Ri) [oc8051_ext_addr_sel.select]
// rd           (out) read from rom [oc8051_pc.rd, oc8051_op_select.rd]
// rd           (out) read from rom [oc8051_pc.rd, oc8051_op_select.rd]
// write_x      (out) write to external rom [pin]
// we_o         (out) write to external rom [pin]
// reti         (out) return from interrupt [pin]
// reti         (out) return from interrupt [pin]
// rmw          (out) read modify write feature [oc8051_ports.rmw]
// rmw          (out) read modify write feature [oc8051_ports.rmw]
//
//
 
 
input clk, rst, eq;
input clk, rst, eq, ack_i;
input [7:0] op_in;
input [7:0] op_in;
 
 
output wr, reti, write_x, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel,
output wr, reti, we_o, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel,
pc_wr, wad2, rmw;
pc_wr, wad2, rmw, stb_o, wr_xaddr;
output [1:0] ram_rd_sel, src_sel1, src_sel2, psw_set, cy_sel, pc_sel, comp_sel;
output [1:0] ram_rd_sel, src_sel1, src_sel2, psw_set, cy_sel, pc_sel, comp_sel;
output [2:0] ram_wr_sel, imm_sel;
output [2:0] ram_wr_sel, imm_sel;
output [3:0] alu_op;
output [3:0] alu_op;
output rd;
output rd;
 
 
reg reti, write_x, rmw;
reg reti, write_x, rmw, stb_buff, we_buff;
reg wr,  bit_addr, src_sel3, rom_addr_sel, ext_addr_sel, pc_wr, wad2;
reg wr,  bit_addr, src_sel3, rom_addr_sel, ext_addr_sel, pc_wr, wad2, stb, stbw, wr_xaddr;
reg [1:0] comp_sel, psw_set, ram_rd_sel, src_sel1, src_sel2, pc_sel, cy_sel;
reg [1:0] comp_sel, psw_set, ram_rd_sel, src_sel1, src_sel2, pc_sel, cy_sel;
reg [3:0] alu_op;
reg [3:0] alu_op;
reg [2:0] ram_wr_sel, imm_sel;
reg [2:0] ram_wr_sel, imm_sel;
 
 
//
//
Line 106... Line 107...
reg [1:0] state;
reg [1:0] state;
reg [7:0] op;
reg [7:0] op;
 
 
//
//
// if state = 2'b00 then read nex instruction
// if state = 2'b00 then read nex instruction
assign rd = !state[0] & !state[1];
assign rd = !state[0] && !state[1] && !stb_o;
 
 
 
assign stb_o = stb_buff || stbw;
 
assign we_o = we_buff;
 
//assign we_o = write_x || we_buff;
 
 
//
//
// main block
// main block
// case of instruction set control signals
// case of instruction set control signals
always @(op_in or eq or state or op)
always @(op_in or eq or state or op or stb_o)
begin
begin
 
  if (stb_o) begin
 
          ram_rd_sel = `OC8051_RRS_DC;
 
          ram_wr_sel = `OC8051_RWS_DC;
 
          src_sel1 = `OC8051_ASS_DC;
 
          src_sel2 = `OC8051_ASS_DC;
 
          alu_op = `OC8051_ALU_NOP;
 
          imm_sel = `OC8051_IDS_DC;
 
          wr = 1'b0;
 
          psw_set = `OC8051_PS_NOT;
 
          cy_sel = `OC8051_CY_0;
 
          pc_wr = `OC8051_PCW_N;
 
          pc_sel = `OC8051_PIS_DC;
 
          src_sel3 = `OC8051_AS3_DC;
 
          comp_sel = `OC8051_CSS_DC;
 
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          wad2 = `OC8051_WAD_N;
 
          rom_addr_sel = `OC8051_RAS_PC;
 
  end else begin
    case (state)
    case (state)
      2'b01: begin
      2'b01: begin
    casex (op)
    casex (op)
      `OC8051_ACALL :begin
      `OC8051_ACALL :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
Line 135... Line 158...
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;
          rmw = `OC8051_RMW_N;
          bit_addr = 1'b0;
          bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_AJMP : begin
      `OC8051_AJMP : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
Line 157... Line 180...
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;
          rmw = `OC8051_RMW_N;
          bit_addr = 1'b0;
          bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_LCALL :begin
      `OC8051_LCALL :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_SP;
          ram_wr_sel = `OC8051_RWS_SP;
Line 179... Line 202...
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;
          rmw = `OC8051_RMW_N;
          bit_addr = 1'b0;
          bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_MOVC_DP :begin
      `OC8051_MOVC_DP :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
Line 199... Line 222...
          src_sel3 = `OC8051_AS3_DP;
          src_sel3 = `OC8051_AS3_DP;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_MOVC_PC :begin
      `OC8051_MOVC_PC :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
Line 219... Line 242...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_DIV : begin
      `OC8051_DIV : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_B;
          ram_wr_sel = `OC8051_RWS_B;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 238... Line 261...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_Y;
          wad2 = `OC8051_WAD_Y;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MUL : begin
      `OC8051_MUL : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_B;
          ram_wr_sel = `OC8051_RWS_B;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 257... Line 280...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_Y;
          wad2 = `OC8051_WAD_Y;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      default begin
      default begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 276... Line 299...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
      end
      end
    endcase
    endcase
    end
    end
    2'b10:
    2'b10:
Line 300... Line 323...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DES;
          comp_sel = `OC8051_CSS_DES;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_CJNE_I : begin
      `OC8051_CJNE_I : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
Line 320... Line 343...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DES;
          comp_sel = `OC8051_CSS_DES;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_CJNE_D : begin
      `OC8051_CJNE_D : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
Line 340... Line 363...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DES;
          comp_sel = `OC8051_CSS_DES;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_CJNE_C : begin
      `OC8051_CJNE_C : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
Line 360... Line 383...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DES;
          comp_sel = `OC8051_CSS_DES;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_DJNZ_R : begin
      `OC8051_DJNZ_R : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
Line 380... Line 403...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DES;
          comp_sel = `OC8051_CSS_DES;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_DJNZ_D : begin
      `OC8051_DJNZ_D : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
Line 400... Line 423...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DES;
          comp_sel = `OC8051_CSS_DES;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_JB : begin
      `OC8051_JB : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
Line 420... Line 443...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_BIT;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_JBC : begin
      `OC8051_JBC : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
Line 440... Line 463...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_BIT;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_JC : begin
      `OC8051_JC : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
Line 460... Line 483...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_CY;
          comp_sel = `OC8051_CSS_CY;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_JMP : begin
      `OC8051_JMP : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
Line 480... Line 503...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_BIT;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_JNB : begin
      `OC8051_JNB : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
Line 500... Line 523...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_BIT;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_JNC : begin
      `OC8051_JNC : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
Line 520... Line 543...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_CY;
          comp_sel = `OC8051_CSS_CY;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_JNZ : begin
      `OC8051_JNZ : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
Line 540... Line 563...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_AZ;
          comp_sel = `OC8051_CSS_AZ;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_JZ : begin
      `OC8051_JZ : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
Line 560... Line 583...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_AZ;
          comp_sel = `OC8051_CSS_AZ;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_MOVC_DP :begin
      `OC8051_MOVC_DP :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
Line 580... Line 603...
          src_sel3 = `OC8051_AS3_DP;
          src_sel3 = `OC8051_AS3_DP;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_DES;
          rom_addr_sel = `OC8051_RAS_DES;
          ext_addr_sel = `OC8051_EAS_DC;
 
 
 
        end
        end
      `OC8051_MOVC_PC :begin
      `OC8051_MOVC_PC :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
Line 600... Line 623...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_DES;
          rom_addr_sel = `OC8051_RAS_DES;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_SJMP : begin
      `OC8051_SJMP : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 619... Line 642...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_DIV : begin
      `OC8051_DIV : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_B;
          ram_wr_sel = `OC8051_RWS_B;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 638... Line 661...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MUL : begin
      `OC8051_MUL : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_B;
          ram_wr_sel = `OC8051_RWS_B;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 657... Line 680...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      default begin
      default begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 676... Line 699...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
      end
      end
    endcase
    endcase
 
 
    2'b11:
    2'b11:
    casex (op)
    casex (op)
Line 699... Line 722...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_CJNE_I : begin
      `OC8051_CJNE_I : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 718... Line 741...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_CJNE_D : begin
      `OC8051_CJNE_D : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 737... Line 760...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_CJNE_C : begin
      `OC8051_CJNE_C : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 756... Line 779...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_DJNZ_R : begin
      `OC8051_DJNZ_R : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 775... Line 798...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_DJNZ_D : begin
      `OC8051_DJNZ_D : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 794... Line 817...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_RET : begin
      `OC8051_RET : begin
          ram_rd_sel = `OC8051_RRS_SP;
          ram_rd_sel = `OC8051_RRS_SP;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 813... Line 836...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_RETI : begin
      `OC8051_RETI : begin
          ram_rd_sel = `OC8051_RRS_SP;
          ram_rd_sel = `OC8051_RRS_SP;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 832... Line 855...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_DIV : begin
      `OC8051_DIV : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_B;
          ram_wr_sel = `OC8051_RWS_B;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 851... Line 874...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MUL : begin
      `OC8051_MUL : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_B;
          ram_wr_sel = `OC8051_RWS_B;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 870... Line 893...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
     default begin
     default begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 889... Line 912...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
      end
      end
    endcase
    endcase
    default: begin
    default: begin
    casex (op_in)
    casex (op_in)
      `OC8051_ACALL :begin
      `OC8051_ACALL :begin
Line 911... Line 934...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_AJMP : begin
      `OC8051_AJMP : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 930... Line 953...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ADD_R : begin
      `OC8051_ADD_R : begin
          ram_rd_sel = `OC8051_RRS_RN;
          ram_rd_sel = `OC8051_RRS_RN;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 949... Line 972...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ADDC_R : begin
      `OC8051_ADDC_R : begin
          ram_rd_sel = `OC8051_RRS_RN;
          ram_rd_sel = `OC8051_RRS_RN;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 968... Line 991...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ANL_R : begin
      `OC8051_ANL_R : begin
          ram_rd_sel = `OC8051_RRS_RN;
          ram_rd_sel = `OC8051_RRS_RN;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 987... Line 1010...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_CJNE_R : begin
      `OC8051_CJNE_R : begin
          ram_rd_sel = `OC8051_RRS_RN;
          ram_rd_sel = `OC8051_RRS_RN;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1006... Line 1029...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_DEC_R : begin
      `OC8051_DEC_R : begin
          ram_rd_sel = `OC8051_RRS_RN;
          ram_rd_sel = `OC8051_RRS_RN;
          ram_wr_sel = `OC8051_RWS_RN;
          ram_wr_sel = `OC8051_RWS_RN;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1025... Line 1048...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_DJNZ_R : begin
      `OC8051_DJNZ_R : begin
          ram_rd_sel = `OC8051_RRS_RN;
          ram_rd_sel = `OC8051_RRS_RN;
          ram_wr_sel = `OC8051_RWS_RN;
          ram_wr_sel = `OC8051_RWS_RN;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1044... Line 1067...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_INC_R : begin
      `OC8051_INC_R : begin
          ram_rd_sel = `OC8051_RRS_RN;
          ram_rd_sel = `OC8051_RRS_RN;
          ram_wr_sel = `OC8051_RWS_RN;
          ram_wr_sel = `OC8051_RWS_RN;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1063... Line 1086...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOV_R : begin
      `OC8051_MOV_R : begin
          ram_rd_sel = `OC8051_RRS_RN;
          ram_rd_sel = `OC8051_RRS_RN;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1082... Line 1105...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
 
 
      `OC8051_MOV_AR : begin
      `OC8051_MOV_AR : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_RN;
          ram_wr_sel = `OC8051_RWS_RN;
Line 1102... Line 1125...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOV_DR : begin
      `OC8051_MOV_DR : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_RN;
          ram_wr_sel = `OC8051_RWS_RN;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1121... Line 1144...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOV_CR : begin
      `OC8051_MOV_CR : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_RN;
          ram_wr_sel = `OC8051_RWS_RN;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 1140... Line 1163...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOV_RD : begin
      `OC8051_MOV_RD : begin
          ram_rd_sel = `OC8051_RRS_RN;
          ram_rd_sel = `OC8051_RRS_RN;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1159... Line 1182...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ORL_R : begin
      `OC8051_ORL_R : begin
          ram_rd_sel = `OC8051_RRS_RN;
          ram_rd_sel = `OC8051_RRS_RN;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1178... Line 1201...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_SUBB_R : begin
      `OC8051_SUBB_R : begin
          ram_rd_sel = `OC8051_RRS_RN;
          ram_rd_sel = `OC8051_RRS_RN;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 1197... Line 1220...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_XCH_R : begin
      `OC8051_XCH_R : begin
          ram_rd_sel = `OC8051_RRS_RN;
          ram_rd_sel = `OC8051_RRS_RN;
          ram_wr_sel = `OC8051_RWS_RN;
          ram_wr_sel = `OC8051_RWS_RN;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1216... Line 1239...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_Y;
          wad2 = `OC8051_WAD_Y;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_XRL_R : begin
      `OC8051_XRL_R : begin
          ram_rd_sel = `OC8051_RRS_RN;
          ram_rd_sel = `OC8051_RRS_RN;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1235... Line 1258...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
 
 
//op_code [7:1]
//op_code [7:1]
      `OC8051_ADD_I : begin
      `OC8051_ADD_I : begin
          ram_rd_sel = `OC8051_RRS_I;
          ram_rd_sel = `OC8051_RRS_I;
Line 1256... Line 1279...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ADDC_I : begin
      `OC8051_ADDC_I : begin
          ram_rd_sel = `OC8051_RRS_I;
          ram_rd_sel = `OC8051_RRS_I;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 1275... Line 1298...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ANL_I : begin
      `OC8051_ANL_I : begin
          ram_rd_sel = `OC8051_RRS_I;
          ram_rd_sel = `OC8051_RRS_I;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 1294... Line 1317...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_CJNE_I : begin
      `OC8051_CJNE_I : begin
          ram_rd_sel = `OC8051_RRS_I;
          ram_rd_sel = `OC8051_RRS_I;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1313... Line 1336...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_DEC_I : begin
      `OC8051_DEC_I : begin
          ram_rd_sel = `OC8051_RRS_I;
          ram_rd_sel = `OC8051_RRS_I;
          ram_wr_sel = `OC8051_RWS_I;
          ram_wr_sel = `OC8051_RWS_I;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1332... Line 1355...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_INC_I : begin
      `OC8051_INC_I : begin
          ram_rd_sel = `OC8051_RRS_I;
          ram_rd_sel = `OC8051_RRS_I;
          ram_wr_sel = `OC8051_RWS_I;
          ram_wr_sel = `OC8051_RWS_I;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1351... Line 1374...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOV_I : begin
      `OC8051_MOV_I : begin
          ram_rd_sel = `OC8051_RRS_I;
          ram_rd_sel = `OC8051_RRS_I;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1370... Line 1393...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOV_ID : begin
      `OC8051_MOV_ID : begin
          ram_rd_sel = `OC8051_RRS_I;
          ram_rd_sel = `OC8051_RRS_I;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1389... Line 1412...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOV_AI : begin
      `OC8051_MOV_AI : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_I;
          ram_wr_sel = `OC8051_RWS_I;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 1408... Line 1431...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOV_DI : begin
      `OC8051_MOV_DI : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_I;
          ram_wr_sel = `OC8051_RWS_I;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1427... Line 1450...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOV_CI : begin
      `OC8051_MOV_CI : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_I;
          ram_wr_sel = `OC8051_RWS_I;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 1446... Line 1469...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOVX_IA : begin
      `OC8051_MOVX_IA : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_XRAM;
          src_sel1 = `OC8051_ASS_XRAM;
          src_sel2 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b1;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_RI;
 
        end
        end
      `OC8051_MOVX_AI :begin
      `OC8051_MOVX_AI :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 1484... Line 1506...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_RI;
 
        end
        end
      `OC8051_ORL_I : begin
      `OC8051_ORL_I : begin
          ram_rd_sel = `OC8051_RRS_I;
          ram_rd_sel = `OC8051_RRS_I;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1503... Line 1524...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_SUBB_I : begin
      `OC8051_SUBB_I : begin
          ram_rd_sel = `OC8051_RRS_I;
          ram_rd_sel = `OC8051_RRS_I;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 1522... Line 1543...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_XCH_I : begin
      `OC8051_XCH_I : begin
          ram_rd_sel = `OC8051_RRS_I;
          ram_rd_sel = `OC8051_RRS_I;
          ram_wr_sel = `OC8051_RWS_I;
          ram_wr_sel = `OC8051_RWS_I;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1541... Line 1562...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_Y;
          wad2 = `OC8051_WAD_Y;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_XCHD :begin
      `OC8051_XCHD :begin
          ram_rd_sel = `OC8051_RRS_I;
          ram_rd_sel = `OC8051_RRS_I;
          ram_wr_sel = `OC8051_RWS_I;
          ram_wr_sel = `OC8051_RWS_I;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1560... Line 1581...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_Y;
          wad2 = `OC8051_WAD_Y;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_XRL_I : begin
      `OC8051_XRL_I : begin
          ram_rd_sel = `OC8051_RRS_I;
          ram_rd_sel = `OC8051_RRS_I;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1579... Line 1600...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
 
 
//op_code [7:0]
//op_code [7:0]
      `OC8051_ADD_D : begin
      `OC8051_ADD_D : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
Line 1600... Line 1621...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ADD_C : begin
      `OC8051_ADD_C : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 1619... Line 1640...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ADDC_D : begin
      `OC8051_ADDC_D : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 1638... Line 1659...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ADDC_C : begin
      `OC8051_ADDC_C : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 1657... Line 1678...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ANL_D : begin
      `OC8051_ANL_D : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 1676... Line 1697...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ANL_C : begin
      `OC8051_ANL_C : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 1695... Line 1716...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ANL_DD : begin
      `OC8051_ANL_DD : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 1714... Line 1735...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ANL_DC : begin
      `OC8051_ANL_DC : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 1733... Line 1754...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ANL_B : begin
      `OC8051_ANL_B : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 1752... Line 1773...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ANL_NB : begin
      `OC8051_ANL_NB : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 1771... Line 1792...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_CJNE_D : begin
      `OC8051_CJNE_D : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 1790... Line 1811...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_CJNE_C : begin
      `OC8051_CJNE_C : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 1809... Line 1830...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_CLR_A : begin
      `OC8051_CLR_A : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 1828... Line 1849...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_CLR_C : begin
      `OC8051_CLR_C : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 1847... Line 1868...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_CLR_B : begin
      `OC8051_CLR_B : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 1866... Line 1887...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_CPL_A : begin
      `OC8051_CPL_A : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 1885... Line 1906...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_CPL_C : begin
      `OC8051_CPL_C : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 1904... Line 1925...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_CPL_B : begin
      `OC8051_CPL_B : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 1923... Line 1944...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_DA : begin
      `OC8051_DA : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 1942... Line 1963...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_DEC_A : begin
      `OC8051_DEC_A : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 1961... Line 1982...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_DEC_D : begin
      `OC8051_DEC_D : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 1980... Line 2001...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_DIV : begin
      `OC8051_DIV : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_B;
          ram_wr_sel = `OC8051_RWS_B;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 1999... Line 2020...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_DJNZ_D : begin
      `OC8051_DJNZ_D : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 2018... Line 2039...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_INC_A : begin
      `OC8051_INC_A : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 2037... Line 2058...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_INC_D : begin
      `OC8051_INC_D : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 2056... Line 2077...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_INC_DP : begin
      `OC8051_INC_DP : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_DPTR;
          ram_wr_sel = `OC8051_RWS_DPTR;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 2075... Line 2096...
          src_sel3 = `OC8051_AS3_DP;
          src_sel3 = `OC8051_AS3_DP;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_JB : begin
      `OC8051_JB : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 2094... Line 2115...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_BIT;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_JBC :begin
      `OC8051_JBC :begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 2113... Line 2134...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_BIT;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_JC : begin
      `OC8051_JC : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 2132... Line 2153...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_CY;
          comp_sel = `OC8051_CSS_CY;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_JMP : begin
      `OC8051_JMP : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 2151... Line 2172...
          src_sel3 = `OC8051_AS3_DP;
          src_sel3 = `OC8051_AS3_DP;
          comp_sel = `OC8051_CSS_BIT;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_JNB : begin
      `OC8051_JNB : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 2170... Line 2191...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_BIT;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_JNC : begin
      `OC8051_JNC : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 2189... Line 2210...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_CY;
          comp_sel = `OC8051_CSS_CY;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_JNZ :begin
      `OC8051_JNZ :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 2208... Line 2229...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_AZ;
          comp_sel = `OC8051_CSS_AZ;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_JZ : begin
      `OC8051_JZ : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 2227... Line 2248...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_AZ;
          comp_sel = `OC8051_CSS_AZ;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_LCALL :begin
      `OC8051_LCALL :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_SP;
          ram_wr_sel = `OC8051_RWS_SP;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 2246... Line 2267...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_LJMP : begin
      `OC8051_LJMP : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 2265... Line 2286...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOV_D : begin
      `OC8051_MOV_D : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 2284... Line 2305...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOV_C : begin
      `OC8051_MOV_C : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 2303... Line 2324...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
 
 
      `OC8051_MOV_DA : begin
      `OC8051_MOV_DA : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
Line 2323... Line 2344...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOV_DD : begin
      `OC8051_MOV_DD : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_D3;
          ram_wr_sel = `OC8051_RWS_D3;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 2342... Line 2363...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOV_CD : begin
      `OC8051_MOV_CD : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 2361... Line 2382...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOV_BC : begin
      `OC8051_MOV_BC : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 2380... Line 2401...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOV_CB : begin
      `OC8051_MOV_CB : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 2399... Line 2420...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOV_DP : begin  ///***
      `OC8051_MOV_DP : begin  ///***
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DPTR;
          ram_wr_sel = `OC8051_RWS_DPTR;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 2418... Line 2439...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOVC_DP :begin
      `OC8051_MOVC_DP :begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 2437... Line 2458...
          src_sel3 = `OC8051_AS3_DP;
          src_sel3 = `OC8051_AS3_DP;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOVC_PC : begin
      `OC8051_MOVC_PC : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 2456... Line 2477...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_MOVX_PA : begin
      `OC8051_MOVX_PA : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_XRAM;
          src_sel1 = `OC8051_ASS_XRAM;
          src_sel2 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b1;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DPTR;
 
        end
        end
      `OC8051_MOVX_AP : begin
      `OC8051_MOVX_AP : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_XRAM;
          src_sel1 = `OC8051_ASS_XRAM;
Line 2494... Line 2514...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DPTR;
 
        end
        end
      `OC8051_MUL : begin
      `OC8051_MUL : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_B;
          ram_wr_sel = `OC8051_RWS_B;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 2513... Line 2532...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ORL_D : begin
      `OC8051_ORL_D : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 2532... Line 2551...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ORL_C : begin
      `OC8051_ORL_C : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 2551... Line 2570...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ORL_AD : begin
      `OC8051_ORL_AD : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 2570... Line 2589...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ORL_CD : begin
      `OC8051_ORL_CD : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 2589... Line 2608...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ORL_B : begin
      `OC8051_ORL_B : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 2608... Line 2627...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_ORL_NB : begin
      `OC8051_ORL_NB : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 2627... Line 2646...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_POP : begin
      `OC8051_POP : begin
          ram_rd_sel = `OC8051_RRS_SP;
          ram_rd_sel = `OC8051_RRS_SP;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 2646... Line 2665...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_PUSH : begin
      `OC8051_PUSH : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_SP;
          ram_wr_sel = `OC8051_RWS_SP;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 2665... Line 2684...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_RET : begin
      `OC8051_RET : begin
          ram_rd_sel = `OC8051_RRS_SP;
          ram_rd_sel = `OC8051_RRS_SP;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 2684... Line 2703...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_RETI : begin
      `OC8051_RETI : begin
          ram_rd_sel = `OC8051_RRS_SP;
          ram_rd_sel = `OC8051_RRS_SP;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 2703... Line 2722...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_RL : begin
      `OC8051_RL : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 2722... Line 2741...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_RLC : begin
      `OC8051_RLC : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 2741... Line 2760...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_RR : begin
      `OC8051_RR : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 2760... Line 2779...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_RRC : begin
      `OC8051_RRC : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 2779... Line 2798...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_SETB_C : begin
      `OC8051_SETB_C : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 2798... Line 2817...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_SETB_B : begin
      `OC8051_SETB_B : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 2817... Line 2836...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_SJMP : begin
      `OC8051_SJMP : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 2836... Line 2855...
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_SUBB_D : begin
      `OC8051_SUBB_D : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 2855... Line 2874...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_SUBB_C : begin
      `OC8051_SUBB_C : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 2874... Line 2893...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_SWAP : begin
      `OC8051_SWAP : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
Line 2893... Line 2912...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_Y;
          wad2 = `OC8051_WAD_Y;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_XCH_D : begin
      `OC8051_XCH_D : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 2912... Line 2931...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_Y;
          wad2 = `OC8051_WAD_Y;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_XRL_D : begin
      `OC8051_XRL_D : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 2931... Line 2950...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_XRL_C : begin
      `OC8051_XRL_C : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 2950... Line 2969...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_XRL_AD : begin
      `OC8051_XRL_AD : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel1 = `OC8051_ASS_RAM;
Line 2969... Line 2988...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      `OC8051_XRL_CD : begin
      `OC8051_XRL_CD : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_D;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
Line 2988... Line 3007...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
        end
        end
      default: begin
      default: begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 3007... Line 3026...
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
 
       end
       end
 
 
    endcase
    endcase
    end
    end
    endcase
    endcase
end
end
 
end
 
 
//
//
// remember current instruction
// remember current instruction
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
  if (rst) op <= #1 2'b00;
  if (rst) op <= #1 2'b00;
Line 3067... Line 3087...
  end
  end
end
end
 
 
//
//
//in case of reti
//in case of reti
always @(posedge clk)
always @(posedge clk or posedge rst)
  if (op==`OC8051_RETI) reti <= #1 1'b1;
  if (rst) reti <= #1 1'b0;
 
  else if (op==`OC8051_RETI) reti <= #1 1'b1;
  else reti <= #1 1'b0;
  else reti <= #1 1'b0;
 
 
//
//
//in case of writing to external ram
//in case of writing to external ram
always @(op_in or rst or rd)
always @(op_in or rd)
begin
begin
  if (rst)
  if (rd)
 
  begin
 
    casex (op_in)
 
      `OC8051_MOVX_AI : begin
 
        stb = 1'b0;
 
        write_x = 1'b1;
 
      end
 
      `OC8051_MOVX_AP : begin
 
        stb = 1'b0;
 
        write_x = 1'b1;
 
      end
 
      `OC8051_MOVX_IA : begin
 
        stb = 1'b1;
 
        write_x = 1'b0;
 
      end
 
      `OC8051_MOVX_PA : begin
 
        stb = 1'b1;
 
        write_x = 1'b0;
 
      end
 
      default : begin
 
        stb = 1'b0;
 
        write_x = 1'b0;
 
      end
 
    endcase
 
  end else begin
    write_x = 1'b0;
    write_x = 1'b0;
  else if (rd)
    stb =1'b0;
 
  end
 
end
 
 
 
always @(op_in)
  begin
  begin
    casex (op_in)
    casex (op_in)
      `OC8051_MOVX_AI : write_x = 1'b1;
    `OC8051_MOVX_AI : begin
      `OC8051_MOVX_AP : write_x = 1'b1;
      ext_addr_sel = `OC8051_EAS_RI;
      default : write_x = 1'b0;
      wr_xaddr = 1'b1;
 
    end
 
    `OC8051_MOVX_AP : begin
 
      ext_addr_sel =  `OC8051_EAS_DPTR;
 
      wr_xaddr = 1'b1;
 
    end
 
    `OC8051_MOVX_IA : begin
 
      ext_addr_sel = `OC8051_EAS_RI;
 
      wr_xaddr = 1'b1;
 
    end
 
    `OC8051_MOVX_PA : begin
 
      ext_addr_sel = `OC8051_EAS_DPTR;
 
      wr_xaddr = 1'b1;
 
    end
 
    default: begin
 
      wr_xaddr = 1'b0;
 
      ext_addr_sel = `OC8051_EAS_DPTR;
 
    end
    endcase
    endcase
  end else write_x = 1'b0;
end
 
 
 
 
 
 
 
always @(posedge clk or posedge rst)
 
begin
 
  if (rst) begin
 
    stbw <= #1 1'b0;
 
  end else
 
    stbw <= #1 write_x;
 
end
 
 
 
 
 
always @(posedge clk or posedge rst)
 
begin
 
  if (rst) begin
 
    stb_buff <= #1 1'b0;
 
    we_buff <= #1 1'b0;
 
  end else if (ack_i) begin
 
    stb_buff <= #1 1'b0;
 
    we_buff <= #1 1'b0;
 
  end else if (stb || stbw) begin
 
    stb_buff <= #1 1'b1;
 
  end else if (write_x) begin
 
    we_buff <= #1 1'b1;
 
  end
end
end
 
 
 
 
endmodule
endmodule
 
 

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