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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_dptr.v] - Diff between revs 46 and 82

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Rev 46 Rev 82
Line 42... Line 42...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.2  2002/09/30 17:33:59  simont
 
// prepared header
 
//
//
//
 
 
// synopsys translate_off
// synopsys translate_off
`include "oc8051_timescale.v"
`include "oc8051_timescale.v"
// synopsys translate_on
// synopsys translate_on
 
 
`include "oc8051_defines.v"
`include "oc8051_defines.v"
 
 
 
 
module oc8051_dptr(clk, rst, addr, data_in, data2_in, wr, wd2, wr_bit, data_hi, data_lo);
module oc8051_dptr(clk, rst, addr, data_in, data2_in, wr, wr_sfr, wr_bit, data_hi, data_lo);
//
//
// clk          (in)  clock
// clk          (in)  clock
// rst          (in)  reset
// rst          (in)  reset
// addr         (in)  write address input [oc8051_ram_wr_sel.out]
// addr         (in)  write address input [oc8051_ram_wr_sel.out]
// data_in      (in)  destination 1 from alu [oc8051_alu.des1]
// data_in      (in)  destination 1 from alu [oc8051_alu.des1]
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// data_lo      (out) output (low bits) [oc8051_ext_addr_sel.dptr_lo]
// data_lo      (out) output (low bits) [oc8051_ext_addr_sel.dptr_lo]
//
//
 
 
 
 
input clk, rst, wr, wr_bit;
input clk, rst, wr, wr_bit;
input [2:0] wd2;
input [2:0] wr_sfr;
input [7:0] addr, data_in, data2_in;
input [7:0] addr, data_in, data2_in;
 
 
output [7:0] data_hi, data_lo;
output [7:0] data_hi, data_lo;
 
 
reg [7:0] data_hi, data_lo;
reg [7:0] data_hi, data_lo;
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always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
begin
begin
  if (rst) begin
  if (rst) begin
    data_hi <= #1 `OC8051_RST_DPH;
    data_hi <= #1 `OC8051_RST_DPH;
    data_lo <= #1 `OC8051_RST_DPL;
    data_lo <= #1 `OC8051_RST_DPL;
  end else if (wd2==`OC8051_RWS_DPTR) begin
  end else if (wr_sfr==`OC8051_WRS_DPTR) begin
//
//
//write from destination 2 and 1
//write from destination 2 and 1
    data_hi <= #1 data2_in;
    data_hi <= #1 data2_in;
    data_lo <= #1 data_in;
    data_lo <= #1 data_in;
  end else if ((addr==`OC8051_SFR_DPTR_HI) & (wr) & !(wr_bit))
  end else if ((addr==`OC8051_SFR_DPTR_HI) & (wr) & !(wr_bit))

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