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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/10/23 16:55:36 simont
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// fix bugs in instruction interface
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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Line 85... |
// cyc_o (out) cycle
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// cyc_o (out) cycle
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input ack_i;
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input ack_i;
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input [31:0] dat_i;
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input [31:0] dat_i;
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output stb_o, cyc_o;
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output stb_o, cyc_o;
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output [15:0] adr_o;
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output [15:0] adr_o;
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reg [15:0] adr_o;
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//reg [15:0] adr_o;
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reg stb_o, cyc_o;
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reg stb_o, cyc_o;
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parameter ADR_WIDTH = 6; // cache address wihth
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parameter LINE_WIDTH = 2; // line address width (2 => 4x32)
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parameter BL_WIDTH = ADR_WIDTH - LINE_WIDTH; // block address width
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parameter BL_NUM = 15; // number of blocks (2^BL_WIDTH-1)
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parameter CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
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//
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//
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// internal buffers adn wires
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// internal buffers adn wires
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//
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//
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// con_buf control buffer
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// con_buf control buffer, contains upper addresses [15:ADDR_WIDTH1] in cache
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reg [13-ADR_WIDTH:0] con_buf [BL_NUM:0];
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// viald[x]=1 if block x is vaild;
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reg [BL_NUM:0] vaild;
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// con0, con2 contain temporal control information of current address and corrent address+2
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// con0, con2 contain temporal control information of current address and corrent address+2
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reg [7:0] con_buf [15:0];
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// part of con_buf memory
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reg [15:0] vaild;
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reg [14-ADR_WIDTH:0] con0, con2;
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reg [8:0] con0, con2;
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//current upper address,
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reg [7:0] cadr0, cadr2;
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reg [13-ADR_WIDTH:0] cadr0, cadr2;
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reg stb_b;
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reg stb_b;
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// byte_select in 32 bit line (adr_i[1:0])
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reg [1:0] byte_sel;
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reg [1:0] byte_sel;
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reg [1:0] cyc;
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// read cycle
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reg [LINE_WIDTH-1:0] cyc;
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// data input from cache ram
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reg [31:0] data1_i;
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reg [31:0] data1_i;
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// temporaly data from ram
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reg [15:0] tmp_data1;
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reg [15:0] tmp_data1;
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reg wr1, wr1_t, stb_it;
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reg wr1, wr1_t, stb_it;
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wire [31:0] data0, data1_o;
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wire [31:0] data0, data1_o;
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wire cy, cy1;
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wire cy, cy1;
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wire [3:0] adr_i2;
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wire [BL_WIDTH-1:0] adr_i2;
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wire hit, hit_l, hit_h;
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wire hit, hit_l, hit_h;
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wire [5:0] adr_r, addr1;
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wire [ADR_WIDTH-1:0] adr_r, addr1;
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reg [5:0] adr_w;
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reg [ADR_WIDTH-1:0] adr_w;
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reg [15:0] mis_adr;
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reg [15:0] mis_adr;
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wire [15:0] data1;
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wire [15:0] data1;
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wire [1:0] adr_r1;
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wire [LINE_WIDTH-1:0] adr_r1;
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assign cy = &adr_i[3:1];
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assign cy = &adr_i[LINE_WIDTH+1:1];
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assign {cy1, adr_i2} = {1'b0, adr_i[7:4]}+{4'b0000, cy};
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assign {cy1, adr_i2} = {1'b0, adr_i[ADR_WIDTH+1:LINE_WIDTH+2]}+cy;
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assign hit_l =(con0=={cadr0,1'b1});
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assign hit_l =(con0=={cadr0,1'b1});
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assign hit_h =(con2=={cadr2,1'b1});
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assign hit_h =(con2=={cadr2,1'b1});
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assign hit = hit_l && hit_h;
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assign hit = hit_l && hit_h;
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assign adr_r = adr_i[7:2] + {5'b00000, adr_i[1]};
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assign adr_r = adr_i[ADR_WIDTH+1:2] + adr_i[1];
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assign addr1 = wr1 ? adr_w : adr_r;
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assign addr1 = wr1 ? adr_w : adr_r;
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assign adr_r1 = adr_r[1:0] + 2'b01;
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assign adr_r1 = adr_r[LINE_WIDTH-1:0] + 2'b01;
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//assign ack_o = hit;
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//assign ack_o = hit;
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assign ack_o = hit && stb_it;
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assign ack_o = hit && stb_it;
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assign data1 = wr1_t ? tmp_data1 : data1_o[31:16];
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assign data1 = wr1_t ? tmp_data1 : data1_o[31:16];
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oc8051_cache_ram oc8051_cache_ram1(.clk(clk), .rst(rst), .addr0(adr_i[7:2]),
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assign adr_o = {mis_adr[15:LINE_WIDTH+2], cyc, 2'b00};
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oc8051_cache_ram oc8051_cache_ram1(.clk(clk), .rst(rst), .addr0(adr_i[ADR_WIDTH+1:2]),
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.addr1(addr1), .data0(data0), .data1_o(data1_o), .data1_i(data1_i),
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.addr1(addr1), .data0(data0), .data1_o(data1_o), .data1_i(data1_i),
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.wr1(wr1));
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.wr1(wr1));
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defparam oc8051_cache_ram1.ADR_WIDTH = ADR_WIDTH;
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defparam oc8051_cache_ram1.CACHE_RAM = CACHE_RAM;
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always @(stb_b or data0 or data1 or byte_sel)
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always @(stb_b or data0 or data1 or byte_sel)
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begin
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begin
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if (stb_b) begin
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if (stb_b) begin
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case (byte_sel)
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case (byte_sel)
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2'b00: dat_o = data0;
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2'b00: dat_o = data0;
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Line 172... |
begin
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begin
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if (rst) begin
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if (rst) begin
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con0 <= #1 9'h0;
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con0 <= #1 9'h0;
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con2 <= #1 9'h0;
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con2 <= #1 9'h0;
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end else begin
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end else begin
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con0 <= #1 {con_buf[adr_i[7:4]], vaild[adr_i[7:4]]};
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con0 <= #1 {con_buf[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]], vaild[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]]};
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con2 <= #1 {con_buf[adr_i2], vaild[adr_i2]};
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con2 <= #1 {con_buf[adr_i2], vaild[adr_i2]};
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end
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end
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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cadr0 <= #1 8'h00;
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cadr0 <= #1 8'h00;
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cadr2 <= #1 8'h00;
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cadr2 <= #1 8'h00;
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end else begin
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end else begin
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cadr0 <= #1 adr_i[15:8];
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cadr0 <= #1 adr_i[15:ADR_WIDTH+2];
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cadr2 <= #1 adr_i[15:8]+{7'h0, cy1};
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cadr2 <= #1 adr_i[15:ADR_WIDTH+2]+ cy1;
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end
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end
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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stb_b <= #1 1'b0;
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stb_b <= #1 1'b0;
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byte_sel <= #1 1'b0;
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byte_sel <= #1 2'b00;
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end else begin
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end else begin
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stb_b <= #1 stb_i;
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stb_b <= #1 stb_i;
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byte_sel <= #1 adr_i[1:0];
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byte_sel <= #1 adr_i[1:0];
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end
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end
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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cyc <= #1 2'b00;
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cyc <= #1 2'b00;
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adr_o <= #1 16'd0;
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cyc_o <= #1 1'b0;
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cyc_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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data1_i<= #1 32'd0;
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data1_i<= #1 32'd0;
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wr1 <= #1 1'b0;
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wr1 <= #1 1'b0;
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adr_w <= #1 6'd0;
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adr_w <= #1 6'd0;
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vaild <= #1 16'd0;
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vaild <= #1 16'd0;
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end if (stb_b && !hit && !stb_o && !wr1) begin
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end if (stb_b && !hit && !stb_o && !wr1) begin
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cyc <= #1 2'b00;
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cyc <= #1 'd0;
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adr_o <= #1 {mis_adr[15:4], 4'b0000};
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cyc_o <= #1 1'b1;
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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data1_i<= #1 32'h0;
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data1_i<= #1 32'h0;
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wr1 <= #1 1'b0;
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wr1 <= #1 1'b0;
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end if (stb_o && ack_i) begin
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end if (stb_o && ack_i) begin
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data1_i<= #1 dat_i;
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data1_i<= #1 dat_i;
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wr1 <= #1 1'b1;
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wr1 <= #1 1'b1;
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adr_w <= #1 adr_o[7:2];
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adr_w <= #1 adr_o[ADR_WIDTH+1:2];
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case (cyc)
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if (&cyc) begin
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2'b00: begin
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cyc <= #1 2'b01;
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adr_o <= #1 {mis_adr[15:4], 4'b0100};
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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end
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2'b01: begin
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cyc <= #1 2'b10;
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adr_o <= #1 {mis_adr[15:4], 4'b1000};
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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end
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2'b10: begin
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cyc <= #1 2'b11;
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adr_o <= #1 {mis_adr[15:4], 4'b1100};
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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end
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default: begin
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cyc <= #1 2'b00;
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cyc <= #1 2'b00;
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adr_o <= #1 {mis_adr[15:4], 4'b0000};
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cyc_o <= #1 1'b0;
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cyc_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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con_buf[mis_adr[7:4]] <= #1 mis_adr[15:8];
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con_buf[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 mis_adr[15:ADR_WIDTH+2];
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vaild[mis_adr[7:4]] <= #1 1'b1;
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vaild[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 1'b1;
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end else begin
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cyc <= #1 cyc + 1'b1;
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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end
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end
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endcase
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/* end else if (wr1 && (cyc==2'b00)) begin
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/* case (cyc)
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2'b00: begin
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cyc <= #1 2'b01;
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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end
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2'b01: begin
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cyc <= #1 2'b10;
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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end
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2'b10: begin
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cyc <= #1 2'b11;
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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end
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default: begin
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cyc <= #1 2'b00;
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cyc_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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con_buf[mis_adr[7:4]] <= #1 mis_adr[15:8];
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vaild[mis_adr[7:4]] <= #1 1'b1;
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vaild[mis_adr[7:4]] <= #1 1'b1;
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wr1 <= #1 1'b0;*/
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end
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endcase*/
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end else begin
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end else begin
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adr_o <= #1 {mis_adr[15:4], cyc, 2'b00};
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wr1 <= #1 1'b0;
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wr1 <= #1 1'b0;
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end
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end
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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mis_adr <= #1 16'h0000;
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mis_adr <= #1 'd0;
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else if (!hit_l)
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else if (!hit_l)
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mis_adr <= #1 adr_i;
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mis_adr <= #1 adr_i;
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else if (!hit_h)
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else if (!hit_h)
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mis_adr <= #1 adr_i+{16'd2};
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mis_adr <= #1 adr_i+'d2;
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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tmp_data1 <= #1 16'd0;
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tmp_data1 <= #1 'd0;
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else if (!hit_h && wr1 && (cyc==adr_r1))
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else if (!hit_h && wr1 && (cyc==adr_r1))
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tmp_data1 <= #1 dat_i[31:16];
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tmp_data1 <= #1 dat_i[31:16];
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else if (!hit_l && hit_h && wr1)
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else if (!hit_l && hit_h && wr1)
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tmp_data1 <= #1 data1_o[31:16];
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tmp_data1 <= #1 data1_o[31:16];
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end
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end
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