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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/09/30 17:33:59 simont
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// prepared header
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module oc8051_indi_addr (clk, rst, addr, data_in, wr, wr_bit, data_out, sel, bank);
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module oc8051_indi_addr (clk, rst, rd_addr, wr_addr, data_in, wr, wr_bit, rn_out, ri_out, sel, bank);
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//
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//
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// clk (in) clock
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// clk (in) clock
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// rst (in) reset
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// rst (in) reset
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// addr (in) write address [oc8051_ram_wr_sel.out]
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// addr (in) write address [oc8051_ram_wr_sel.out]
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// data_in (in) data input (alu destination1) [oc8051_alu.des1]
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// data_in (in) data input (alu destination1) [oc8051_alu.des1]
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// sel (in) select register [oc8051_op_select.op1_out[0] ]
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// sel (in) select register [oc8051_op_select.op1_out[0] ]
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// bank (in) select register bank: [oc8051_psw.data_out[4:3] ]
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// bank (in) select register bank: [oc8051_psw.data_out[4:3] ]
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//
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//
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input clk, rst, wr, sel, wr_bit;
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input clk, rst, wr, wr_bit;
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input [1:0] bank;
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input [1:0] bank;
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input [7:0] addr, data_in;
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input [2:0] sel;
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input [7:0] data_in;
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input [7:0] rd_addr, wr_addr;
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output [7:0] rn_out, ri_out;
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output [7:0] data_out;
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reg [7:0] rn_out;
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reg [7:0] buff [7:0];
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reg [7:0] buff [31:0];
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reg wr_bit_r;
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wire rd_ram, rd_ind;
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wire tmp;
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assign tmp = ~|wr_addr[7:5];
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//
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//
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//write to buffer
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//write to buffer
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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buff[3'b000] = #1 8'h00;
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buff[0] <= #1 8'h00;
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buff[3'b001] = #1 8'h00;
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buff[1] <= #1 8'h00;
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buff[3'b010] = #1 8'h00;
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buff[2] <= #1 8'h00;
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buff[3'b011] = #1 8'h00;
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buff[3] <= #1 8'h00;
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buff[3'b100] = #1 8'h00;
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buff[4] <= #1 8'h00;
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buff[3'b101] = #1 8'h00;
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buff[5] <= #1 8'h00;
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buff[3'b110] = #1 8'h00;
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buff[6] <= #1 8'h00;
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buff[3'b111] = #1 8'h00;
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buff[7] <= #1 8'h00;
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end else begin
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buff[8] <= #1 8'h00;
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if ((wr) & !(wr_bit)) begin
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buff[9] <= #1 8'h00;
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case (addr)
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buff[10] <= #1 8'h00;
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8'h00: buff[3'b000] = #1 data_in;
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buff[11] <= #1 8'h00;
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8'h01: buff[3'b001] = #1 data_in;
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buff[12] <= #1 8'h00;
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8'h08: buff[3'b010] = #1 data_in;
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buff[13] <= #1 8'h00;
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8'h09: buff[3'b011] = #1 data_in;
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buff[14] <= #1 8'h00;
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8'h10: buff[3'b100] = #1 data_in;
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buff[15] <= #1 8'h00;
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8'h11: buff[3'b101] = #1 data_in;
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buff[16] <= #1 8'h00;
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8'h18: buff[3'b110] = #1 data_in;
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buff[17] <= #1 8'h00;
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8'h19: buff[3'b111] = #1 data_in;
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buff[18] <= #1 8'h00;
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endcase
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buff[19] <= #1 8'h00;
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end
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buff[20] <= #1 8'h00;
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buff[21] <= #1 8'h00;
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buff[22] <= #1 8'h00;
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buff[23] <= #1 8'h00;
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buff[24] <= #1 8'h00;
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buff[25] <= #1 8'h00;
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buff[26] <= #1 8'h00;
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buff[27] <= #1 8'h00;
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buff[28] <= #1 8'h00;
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buff[29] <= #1 8'h00;
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buff[30] <= #1 8'h00;
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buff[31] <= #1 8'h00;
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end else if ((wr) && !(wr_bit_r) && (tmp)) begin
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buff[wr_addr[4:0]] <= #1 data_in;
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end
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end
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end
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end
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//
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//
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//read from buffer
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//read from buffer
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assign data_out = (({3'b000, bank, 2'b00, sel}==addr) & (wr)) ?
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assign rd_ram = (rd_addr== wr_addr);
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data_in : buff[{bank, sel}];
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assign rd_ind = ({3'h0, bank, 2'b00, sel[0]}==wr_addr);
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assign ri_out = ( rd_ind & (wr) & !wr_bit) ? data_in : buff[{bank, 2'b00, sel[0]}];
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always @(posedge clk or posedge rst)
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if (rst) begin
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rn_out <= #1 8'h00;
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end else if ( rd_ram & (wr) & !wr_bit) begin
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rn_out <= #1 data_in;
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end else begin
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rn_out <= #1 buff[rd_addr[4:0]];
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end
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always @(posedge clk or posedge rst)
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if (rst) begin
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wr_bit_r <= #1 1'b0;
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end else begin
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wr_bit_r <= #1 wr_bit;
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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