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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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//synopsys translate_on
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//synopsys translate_on
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module oc0851_int (clk, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit, tf0, tf1, int, ie0, ie1, rst, reti, int_vec, tr0, tr1, uart, ack);
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module oc0851_int (clk, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit, tf0, tf1, intr, ie0, ie1, rst, reti, int_vec, tr0, tr1, uart, ack);
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input [7:0] wr_addr, data_in, rd_addr;
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input [7:0] wr_addr, data_in, rd_addr;
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input wr, tf0, tf1, ie0, ie1, clk, rst, reti, wr_bit, bit_in, uart, ack;
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input wr, tf0, tf1, ie0, ie1, clk, rst, reti, wr_bit, bit_in, uart, ack;
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output tr0, tr1, int, bit_out;
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output tr0, tr1, intr, bit_out;
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output [7:0] int_vec, data_out;
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output [7:0] int_vec, data_out;
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reg [7:0] ip, ie, int_vec, id, data_out;
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reg [7:0] ip, ie, int_vec, id, data_out;
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reg [3:0] tcon_s;
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reg [3:0] tcon_s;
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// int_l0 waiting interrupts on level 0
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// int_l0 waiting interrupts on level 0
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// int_l1 waiting interrupts on level 1
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// int_l1 waiting interrupts on level 1
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wire [4:0] int_l0, int_l1;
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wire [4:0] int_l0, int_l1;
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wire il0, il1;
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wire il0, il1;
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integer n;
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//reg set_tf0, set_tf1, set_ie0, set_ie1;
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//reg set_tf0, set_tf1, set_ie0, set_ie1;
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reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;
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reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;
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//reg tf0_ack, tf1_ack, ie0_ack, ie1_ack;
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//reg tf0_ack, tf1_ack, ie0_ack, ie1_ack;
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assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};
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assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};
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assign tr0 = tcon_s[2];
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assign tr0 = tcon_s[2];
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assign tr1 = tcon_s[3];
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assign tr1 = tcon_s[3];
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assign int = |int_vec;
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assign intr = |int_vec;
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assign int_l0 = ~ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
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assign int_l0 = ~ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
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assign int_l1 = ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
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assign int_l1 = ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
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assign il0 = |int_l0;
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assign il0 = |int_l0;
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assign il1 = |int_l1;
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assign il1 = |int_l1;
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int_vec <= #1 8'h00;
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int_vec <= #1 8'h00;
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end
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end
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end
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end
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always @(posedge clk)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (wr & !wr_bit & (wr_addr==rd_addr) & (
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if (rst) data_out <= #1 8'h0;
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else if (wr & !wr_bit & (wr_addr==rd_addr) & (
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(wr_addr==`OC8051_SFR_IP) | (wr_addr==`OC8051_SFR_IE) | (wr_addr==`OC8051_SFR_TCON))) begin
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(wr_addr==`OC8051_SFR_IP) | (wr_addr==`OC8051_SFR_IE) | (wr_addr==`OC8051_SFR_TCON))) begin
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data_out <= #1 data_in;
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data_out <= #1 data_in;
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end else begin
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end else begin
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case (rd_addr)
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case (rd_addr)
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`OC8051_SFR_IP: data_out <= #1 ip;
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`OC8051_SFR_IP: data_out <= #1 ip;
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default: data_out <= #1 tcon;
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default: data_out <= #1 tcon;
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endcase
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endcase
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end
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end
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end
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end
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always @(posedge clk)
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always @(posedge clk or posedge rst)
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if (rst) begin
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tf0_buff <= #1 1'b0;
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tf1_buff <= #1 1'b0;
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ie0_buff <= #1 1'b0;
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ie1_buff <= #1 1'b0;
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end else begin
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tf0_buff <= #1 tf0;
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tf0_buff <= #1 tf0;
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always @(posedge clk)
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tf1_buff <= #1 tf1;
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tf1_buff <= #1 tf1;
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always @(posedge clk)
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ie0_buff <= #1 ie0;
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ie0_buff <= #1 ie0;
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always @(posedge clk)
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ie1_buff <= #1 ie1;
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ie1_buff <= #1 ie1;
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end
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always @(posedge clk)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (wr & wr_bit & (wr_addr==rd_addr) & ((wr_addr[7:3]==`OC8051_SFR_B_IP) |
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if (rst) bit_out <= #1 1'b0;
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else if (wr & wr_bit & (wr_addr==rd_addr) & ((wr_addr[7:3]==`OC8051_SFR_B_IP) |
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(wr_addr[7:3]==`OC8051_SFR_B_IE) | (wr_addr[7:3]==`OC8051_SFR_B_TCON))) begin
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(wr_addr[7:3]==`OC8051_SFR_B_IE) | (wr_addr[7:3]==`OC8051_SFR_B_TCON))) begin
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bit_out <= #1 bit_in;
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bit_out <= #1 bit_in;
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end else begin
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end else begin
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case (rd_addr[7:3])
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case (rd_addr[7:3])
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`OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
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`OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
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