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Line 44... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/09/30 17:33:59 simont
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// prepared header
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//
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//
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//
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//clk clock (pin)
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//rst reset (pin)
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//wr_addr address for selecting different registers (input)
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//data_in data input (input)
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//wr read/write signal (input)
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//tf0 signal for timer interrupt 0 (input)
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//tf1 signal for timer interrupt 1 (input)
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//ie0 signal for external interrupt 0 (input)
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//ie1 signal for external interrupt 1 (input)
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//reti return from interrupt signal (input)
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//int_src describes interrupt source (output)
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//ip ip register (internal)
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//ie ie register (internal)
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//tcon tcon register (internal)
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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//synopsys translate_off
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//synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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//synopsys translate_on
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//synopsys translate_on
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module oc0851_int (clk, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit, tf0, tf1, intr, ie0, ie1, rst, reti, int_vec, tr0, tr1, uart, ack);
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module oc0851_int (clk, rst, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit,
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//timer interrupts
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tf0, tf1, t2_int,
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tr0, tr1,
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//external interrupts
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ie0, ie1,
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//uart interrupts
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uart_int,
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//to cpu
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intr, reti, int_vec, ack);
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input [7:0] wr_addr, data_in, rd_addr;
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input [7:0] wr_addr, data_in, rd_addr;
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input wr, tf0, tf1, ie0, ie1, clk, rst, reti, wr_bit, bit_in, uart, ack;
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input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;
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output tr0, tr1, intr, bit_out;
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output tr0, tr1, intr, bit_out;
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output [7:0] int_vec, data_out;
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output [7:0] int_vec, data_out;
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reg [7:0] ip, ie, int_vec, data_out;
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reg [7:0] ip, ie, int_vec, data_out;
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| Line 88... |
Line 82... |
reg [3:0] tcon_s;
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reg [3:0] tcon_s;
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reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;
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reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;
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wire [7:0] tcon;
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wire [7:0] tcon;
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//
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//
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// isrc_cur current interrupt source
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// isrc processing interrupt sources
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// isrc_w waiting interrupt source
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// int_dept
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reg [2:0] isrc_cur, isrc_w;
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wire [2:0] isrc_cur;
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reg [2:0] isrc [1:0];
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reg int_dept;
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wire int_dept_1;
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reg int_proc;
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reg [1:0] int_lev [1:0];
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wire cur_lev;
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assign isrc_cur = int_proc ? isrc[int_dept_1] : 2'h0;
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assign int_dept_1 = int_dept - 1'b1;
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assign cur_lev = int_lev[int_dept_1];
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//
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//
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// contains witch level of interrupts is running
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// contains witch level of interrupts is running
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reg [1:0] int_levl, int_levl_w;
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//reg [1:0] int_levl, int_levl_w;
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//
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//
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// int_l0 waiting interrupts on level 0
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// int_ln waiting interrupts on level n
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// int_l1 waiting interrupts on level 1
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// ip_ln interrupts on level n
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wire [4:0] int_l0, int_l1;
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// int_src interrupt sources
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wire [5:0] int_l0, int_l1;
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wire [5:0] ip_l0, ip_l1;
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wire [5:0] int_src;
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wire il0, il1;
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wire il0, il1;
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//reg set_tf0, set_tf1, set_ie0, set_ie1;
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reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;
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reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;
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//reg tf0_ack, tf1_ack, ie0_ack, ie1_ack;
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//
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//interrupt priority
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assign ip_l0 = ~ip[5:0];
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assign ip_l1 = ip[5:0];
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assign int_src = {t2_int, uart_int, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
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//
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// waiting interrupts
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assign int_l0 = ip_l0 & {ie[5:0]} & int_src;
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assign int_l1 = ip_l1 & {ie[5:0]} & int_src;
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assign il0 = |int_l0;
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assign il1 = |int_l1;
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//
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// TCON
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assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};
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assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};
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assign tr0 = tcon_s[2];
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assign tr0 = tcon_s[2];
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assign tr1 = tcon_s[3];
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assign tr1 = tcon_s[3];
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assign intr = |int_vec;
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assign intr = |int_vec;
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assign int_l0 = ~ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
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assign int_l1 = ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
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assign il0 = |int_l0;
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assign il1 = |int_l1;
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//
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// IP
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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ip <=#1 `OC8051_RST_IP;
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ip <=#1 `OC8051_RST_IP;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
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ip <= #1 data_in;
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ip <= #1 data_in;
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
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ip[wr_addr[2:0]] <= #1 bit_in;
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ip[wr_addr[2:0]] <= #1 bit_in;
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end
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end
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//
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// IE
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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ie <=#1 `OC8051_RST_IE;
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ie <=#1 `OC8051_RST_IE;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
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| Line 142... |
Line 164... |
// tcon_s
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// tcon_s
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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// tcon_s <=#1 {`OC8051_RST_TCON[6], `OC8051_RST_TCON[4], `OC8051_RST_TCON[2], `OC8051_RST_TCON[0]};
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tcon_s <=#1 4'b0000;
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tcon_s <=#1 4'b0000;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
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tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
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case (wr_addr[2:0])
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case (wr_addr[2:0])
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Line 183... |
// tf1 (tmod.7)
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// tf1 (tmod.7)
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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// tcon_tf1 <=#1 `OC8051_RST_TCON[7];
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tcon_tf1 <=#1 1'b0;
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tcon_tf1 <=#1 1'b0;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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tcon_tf1 <= #1 data_in[7];
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tcon_tf1 <= #1 data_in[7];
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
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tcon_tf1 <= #1 bit_in;
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tcon_tf1 <= #1 bit_in;
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Line 201... |
// tf0 (tmod.5)
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// tf0 (tmod.5)
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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// tcon_tf0 <=#1 `OC8051_RST_TCON[5];
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tcon_tf0 <=#1 1'b0;
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tcon_tf0 <=#1 1'b0;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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tcon_tf0 <= #1 data_in[5];
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tcon_tf0 <= #1 data_in[5];
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
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tcon_tf0 <= #1 bit_in;
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tcon_tf0 <= #1 bit_in;
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Line 220... |
// ie0 (tmod.1)
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// ie0 (tmod.1)
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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// tcon_ie0 <=#1 `OC8051_RST_TCON[1];
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tcon_ie0 <=#1 1'b0;
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tcon_ie0 <=#1 1'b0;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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tcon_ie0 <= #1 data_in[1];
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tcon_ie0 <= #1 data_in[1];
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
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tcon_ie0 <= #1 bit_in;
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tcon_ie0 <= #1 bit_in;
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| Line 238... |
Line 256... |
end else if (!(tcon_s[1]) & (ie1)) begin
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end else if (!(tcon_s[1]) & (ie1)) begin
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tcon_ie1 <= #1 1'b0;
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tcon_ie1 <= #1 1'b0;
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end
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end
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end
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end
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//
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// interrupt processing
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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int_vec <= #1 8'h00;
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int_vec <= #1 8'h00;
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isrc_cur <= #1 `OC8051_ISRC_NO;
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int_dept <= #1 1'b0;
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isrc_w <= #1 `OC8051_ISRC_NO;
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isrc[0] <= #1 3'h0;
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int_levl <= #1 `OC8051_ILEV_NO;
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isrc[1] <= #1 3'h0;
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int_levl_w <= #1 `OC8051_ILEV_NO;
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int_proc <= #1 1'b0;
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int_lev[0] <= #1 1'b0;
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int_lev[1] <= #1 1'b0;
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end else if (reti) begin // return from interrupt
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end else if (reti) begin // return from interrupt
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isrc_cur <= #1 isrc_w;
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if (int_dept==2'b01)
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int_levl <= #1 int_levl_w;
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int_proc <= #1 1'b0;
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end else if ((ie[7]) & (int_levl!=`OC8051_ILEV_L1) & (il1)) begin // interrupt on level 1
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int_dept <= #1 int_dept - 2'b01;
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isrc_w <= #1 isrc_cur;
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end else if (((ie[7]) & (!cur_lev) || !int_proc) & il1) begin // interrupt on level 1
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int_levl <= #1 `OC8051_ILEV_L1;
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int_proc <= #1 1'b1;
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int_levl_w <= #1 int_levl;
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int_lev[int_dept] <= #1 `OC8051_ILEV_L1;
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int_dept <= #1 int_dept + 2'b01;
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if (int_l1[0]) begin
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if (int_l1[0]) begin
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int_vec <= #1 `OC8051_INT_X0;
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int_vec <= #1 `OC8051_INT_X0;
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isrc_cur <= #1 `OC8051_ISRC_IE0;
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isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
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end else if (int_l1[1]) begin
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end else if (int_l1[1]) begin
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int_vec <= #1 `OC8051_INT_T0;
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int_vec <= #1 `OC8051_INT_T0;
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isrc_cur <= #1 `OC8051_ISRC_TF0;
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isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
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end else if (int_l1[2]) begin
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end else if (int_l1[2]) begin
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int_vec <= #1 `OC8051_INT_X1;
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int_vec <= #1 `OC8051_INT_X1;
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isrc_cur <= #1 `OC8051_ISRC_IE1;
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isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
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end else if (int_l1[3]) begin
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end else if (int_l1[3]) begin
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int_vec <= #1 `OC8051_INT_T1;
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int_vec <= #1 `OC8051_INT_T1;
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isrc_cur <= #1 `OC8051_ISRC_TF1;
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isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
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end else if (int_l1[4]) begin
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end else if (int_l1[4]) begin
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int_vec <= #1 `OC8051_INT_UART;
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int_vec <= #1 `OC8051_INT_UART;
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isrc_cur <= #1 `OC8051_ISRC_UART;
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isrc[int_dept] <= #1 `OC8051_ISRC_UART;
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end else if (int_l1[5]) begin
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int_vec <= #1 `OC8051_INT_T2;
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isrc[int_dept] <= #1 `OC8051_ISRC_T2;
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end
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end
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end else if ((ie[7]) & (int_levl==`OC8051_ILEV_NO) & (il0)) begin // interrupt on level 0
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int_levl <= #1 `OC8051_ILEV_L0;
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end else if ((ie[7]) & !int_proc & il0) begin // interrupt on level 0
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int_proc <= #1 1'b1;
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int_lev[int_dept] <= #1 `OC8051_ILEV_L0;
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int_dept <= #1 int_dept + 2'b01;
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if (int_l0[0]) begin
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if (int_l0[0]) begin
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int_vec <= #1 `OC8051_INT_X0;
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int_vec <= #1 `OC8051_INT_X0;
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isrc_cur <= #1 `OC8051_ISRC_IE0;
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isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
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end else if (int_l0[1]) begin
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end else if (int_l0[1]) begin
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int_vec <= #1 `OC8051_INT_T0;
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int_vec <= #1 `OC8051_INT_T0;
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isrc_cur <= #1 `OC8051_ISRC_TF0;
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isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
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end else if (int_l0[2]) begin
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end else if (int_l0[2]) begin
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int_vec <= #1 `OC8051_INT_X1;
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int_vec <= #1 `OC8051_INT_X1;
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isrc_cur <= #1 `OC8051_ISRC_IE1;
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isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
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end else if (int_l0[3]) begin
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end else if (int_l0[3]) begin
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int_vec <= #1 `OC8051_INT_T1;
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int_vec <= #1 `OC8051_INT_T1;
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isrc_cur <= #1 `OC8051_ISRC_TF1;
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isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
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end else if (int_l0[4]) begin
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end else if (int_l0[4]) begin
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int_vec <= #1 `OC8051_INT_UART;
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int_vec <= #1 `OC8051_INT_UART;
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isrc_cur <= #1 `OC8051_ISRC_UART;
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isrc[int_dept] <= #1 `OC8051_ISRC_UART;
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end else if (int_l0[5]) begin
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int_vec <= #1 `OC8051_INT_T2;
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isrc[int_dept] <= #1 `OC8051_ISRC_T2;
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end
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end
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end else begin
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end else begin
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int_vec <= #1 8'h00;
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int_vec <= #1 8'h00;
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end
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end
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end
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end
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| Line 303... |
Line 334... |
(wr_addr==`OC8051_SFR_IP) | (wr_addr==`OC8051_SFR_IE) | (wr_addr==`OC8051_SFR_TCON))) begin
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(wr_addr==`OC8051_SFR_IP) | (wr_addr==`OC8051_SFR_IE) | (wr_addr==`OC8051_SFR_TCON))) begin
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data_out <= #1 data_in;
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data_out <= #1 data_in;
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end else begin
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end else begin
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case (rd_addr)
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case (rd_addr)
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`OC8051_SFR_IP: data_out <= #1 ip;
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`OC8051_SFR_IP: data_out <= #1 ip;
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`OC8051_SFR_IE: data_out <= #1 ie;
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`OC8051_SFR_IE: data_out <= #1 ie0;
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default: data_out <= #1 tcon;
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default: data_out <= #1 tcon;
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endcase
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endcase
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end
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end
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end
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end
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