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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_memory_interface.v] - Diff between revs 121 and 128
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| Rev 121 |
Rev 128 |
| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2003/04/11 10:05:08 simont
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// Change pc add value from 23'h to 16'h
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//
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// Revision 1.2 2003/04/09 16:24:03 simont
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// Revision 1.2 2003/04/09 16:24:03 simont
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// change wr_sft to 2 bit wire.
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// change wr_sft to 2 bit wire.
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//
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//
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// Revision 1.1 2003/01/13 14:13:12 simont
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// Revision 1.1 2003/01/13 14:13:12 simont
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// initial import
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// initial import
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| Line 316... |
Line 319... |
imem_wait <= #1 1'b0;
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imem_wait <= #1 1'b0;
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idat_ir <= #1 24'h0;
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idat_ir <= #1 24'h0;
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end else if (iack_i) begin
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end else if (iack_i) begin
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istb_t <= #1 1'b0;
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istb_t <= #1 1'b0;
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imem_wait <= #1 1'b0;
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imem_wait <= #1 1'b0;
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idat_ir <= #1 idat_i [31:8];
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idat_ir <= #1 idat_i [23:0];
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end else if (ea_rom_sel && imem_wait) begin
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end else if (ea_rom_sel && imem_wait) begin
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imem_wait <= #1 1'b0;
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imem_wait <= #1 1'b0;
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end else if (ea_rom_sel && !imem_wait && istb_t) begin
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end else if (ea_rom_sel && !imem_wait && istb_t) begin
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istb_t <= #1 1'b0;
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istb_t <= #1 1'b0;
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end else if (mem_act==`OC8051_MAS_CODE) begin
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end else if (mem_act==`OC8051_MAS_CODE) begin
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| Line 406... |
Line 409... |
assign op2_out = (rd) ? op2_o : op2_buff;
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assign op2_out = (rd) ? op2_o : op2_buff;
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always @(idat_i or iack_i or idat_ir or rd)
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always @(idat_i or iack_i or idat_ir or rd)
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begin
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begin
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if (iack_i) begin
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if (iack_i) begin
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op1_xt = idat_i[31:24];
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op1_xt = idat_i[7:0];
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op2_xt = idat_i[23:16];
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op2_xt = idat_i[15:8];
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op3_xt = idat_i[15:8];
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op3_xt = idat_i[23:16];
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end else if (!rd) begin
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end else if (!rd) begin
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op1_xt = idat_ir[23:16];
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op1_xt = idat_ir[7:0];
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op2_xt = idat_ir[15:8];
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op2_xt = idat_ir[15:8];
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op3_xt = idat_ir[7:0];
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op3_xt = idat_ir[23:16];
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end else begin
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end else begin
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op1_xt = 8'h00;
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op1_xt = 8'h00;
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op2_xt = 8'h00;
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op2_xt = 8'h00;
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op3_xt = 8'h00;
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op3_xt = 8'h00;
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end
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end
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