| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2003/05/12 16:27:40 simont
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// fix bug in movc intruction.
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//
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// Revision 1.7 2003/05/06 09:39:34 simont
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// Revision 1.7 2003/05/06 09:39:34 simont
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// cahnge assigment to pc_wait (remove istb_o)
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// cahnge assigment to pc_wait (remove istb_o)
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//
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//
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// Revision 1.6 2003/05/05 15:46:37 simont
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// Revision 1.6 2003/05/05 15:46:37 simont
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// add aditional alu destination to solve critical path.
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// add aditional alu destination to solve critical path.
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| Line 73... |
Line 76... |
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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|
|
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module oc8051_memory_interface (clk, rst,
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module oc8051_memory_interface (clk, rst,
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|
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//decoder
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//decoder
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wr_i, wr_bit_i, rd_sel, wr_sel,
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wr_i,
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pc_wr_sel, pc_wr, pc, rd,
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wr_bit_i,
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mem_wait, mem_act, istb,
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rd_sel,
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//internal ram
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wr_sel,
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wr_o, wr_bit_o, rd_addr, wr_addr, rd_ind, wr_ind, wr_dat,
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pc_wr_sel,
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pc_wr,
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pc,
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rd,
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mem_wait,
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mem_act,
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istb,
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bit_in, in_ram, sfr, sfr_bit, bit_out, iram_out,
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//internal ram
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wr_o,
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wr_bit_o,
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rd_addr,
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wr_addr,
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rd_ind,
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wr_ind,
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wr_dat,
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|
|
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bit_in,
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in_ram,
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sfr,
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sfr_bit,
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bit_out,
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iram_out,
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|
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//program rom
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//program rom
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iadr_o, ea, ea_int,
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iadr_o,
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op1_out, op2_out, op3_out,
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ea,
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ea_int,
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op1_out,
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op2_out,
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op3_out,
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|
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//internal
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//internal
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op1_i, op2_i, op3_i,
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idat_onchip,
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|
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//external
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//external
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iack_i, istb_o, idat_i,
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iack_i,
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istb_o,
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idat_i,
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|
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//external data ram
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//external data ram
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dadr_o, dwe_o, dstb_o, dack_i, ddat_i, ddat_o,
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dadr_o,
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dwe_o,
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dstb_o,
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dack_i,
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ddat_i,
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ddat_o,
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|
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//interrupt interface
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//interrupt interface
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intr, int_v, int_ack,
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intr,
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int_v,
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int_ack,
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|
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//alu
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//alu
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des_acc, des1, des2,
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des_acc,
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des1,
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des2,
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|
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//sfr's
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//sfr's
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dptr, ri, sp, sp_w, rn, acc, reti);
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dptr,
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ri,
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input bit_in, sfr_bit, dack_i;
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sp,
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sp_w,
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rn,
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acc,
|
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reti
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|
);
|
|
|
|
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input clk,
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rst,
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wr_i,
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wr_bit_i;
|
|
|
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input bit_in,
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sfr_bit,
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dack_i;
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input [2:0] mem_act;
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input [2:0] mem_act;
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input [7:0] in_ram, sfr, acc, sp_w;
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input [7:0] in_ram,
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sfr,
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acc,
|
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sp_w;
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input [31:0] idat_i;
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input [31:0] idat_i;
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|
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output bit_out, mem_wait, reti;
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output bit_out,
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output [7:0] iram_out, wr_dat;
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mem_wait,
|
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reti;
|
reg bit_out, reti;
|
output [7:0] iram_out,
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reg [7:0] iram_out, sp_r;
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wr_dat;
|
|
|
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reg bit_out,
|
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reti;
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reg [7:0] iram_out,
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sp_r;
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reg rd_addr_r;
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reg rd_addr_r;
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input clk, rst, wr_i, wr_bit_i;
|
output wr_o,
|
output wr_o, wr_bit_o;
|
wr_bit_o;
|
|
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//????
|
//????
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reg dack_ir;
|
reg dack_ir;
|
reg [7:0] ddat_ir;
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reg [7:0] ddat_ir;
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reg [23:0] idat_ir;
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reg [23:0] idat_ir;
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| Line 126... |
Line 191... |
//
|
//
|
// rom_addr_sel
|
// rom_addr_sel
|
//
|
//
|
/////////////////////////////
|
/////////////////////////////
|
input iack_i;
|
input iack_i;
|
input [7:0] des_acc, des1, des2;
|
input [7:0] des_acc,
|
|
des1,
|
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des2;
|
output [15:0] iadr_o;
|
output [15:0] iadr_o;
|
|
|
wire ea_rom_sel;
|
wire ea_rom_sel;
|
|
|
/////////////////////////////
|
/////////////////////////////
|
//
|
//
|
// ext_addr_sel
|
// ext_addr_sel
|
//
|
//
|
/////////////////////////////
|
/////////////////////////////
|
input [7:0] ri, ddat_i;
|
input [7:0] ri,
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ddat_i;
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input [15:0] dptr;
|
input [15:0] dptr;
|
|
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output dstb_o, dwe_o;
|
output dstb_o,
|
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dwe_o;
|
output [7:0] ddat_o;
|
output [7:0] ddat_o;
|
output [15:0] dadr_o;
|
output [15:0] dadr_o;
|
|
|
/////////////////////////////
|
/////////////////////////////
|
//
|
//
|
// ram_adr_sel
|
// ram_adr_sel
|
//
|
//
|
/////////////////////////////
|
/////////////////////////////
|
|
|
input [2:0] rd_sel, wr_sel;
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input [2:0] rd_sel,
|
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wr_sel;
|
input [4:0] rn;
|
input [4:0] rn;
|
input [7:0] sp;
|
input [7:0] sp;
|
|
|
output rd_ind, wr_ind;
|
output rd_ind,
|
output [7:0] wr_addr, rd_addr;
|
wr_ind;
|
reg rd_ind, wr_ind;
|
output [7:0] wr_addr,
|
reg [7:0] wr_addr, rd_addr;
|
rd_addr;
|
|
reg rd_ind,
|
|
wr_ind;
|
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reg [7:0] wr_addr,
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rd_addr;
|
|
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reg [4:0] rn_r;
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reg [4:0] rn_r;
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reg [7:0] ri_r, imm_r, imm2_r, op1_r;
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reg [7:0] ri_r,
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wire [7:0] imm, imm2;
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imm_r,
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imm2_r,
|
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op1_r;
|
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wire [7:0] imm,
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imm2;
|
|
|
/////////////////////////////
|
/////////////////////////////
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//
|
//
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// op_select
|
// op_select
|
//
|
//
|
/////////////////////////////
|
/////////////////////////////
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input intr, rd, ea, ea_int, istb;
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input intr,
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input [7:0] op1_i, op2_i, op3_i, int_v;
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rd,
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output int_ack, istb_o;
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ea,
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output [7:0] op1_out, op3_out, op2_out;
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ea_int,
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istb;
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input [7:0] int_v;
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input [31:0] idat_onchip;
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output int_ack,
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istb_o;
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output [7:0] op1_out,
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op3_out,
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op2_out;
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reg int_ack_t,
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int_ack,
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int_ack_buff;
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reg int_ack_t, int_ack, int_ack_buff;
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reg [7:0] int_vec_buff;
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reg [7:0] int_vec_buff;
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reg [7:0] op1_out, op2_buff, op3_buff;
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reg [7:0] op1_out,
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reg [7:0] op1_o, op2_o, op3_o;
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op2_buff,
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reg [7:0] op1_xt, op2_xt, op3_xt;
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op3_buff;
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reg [7:0] op1_o,
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wire [7:0] op1, op2, op3, op2_direct;
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op2_o,
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//wire op_sel;
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op3_o;
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reg [7:0] op1_xt,
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op2_xt,
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op3_xt;
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reg [7:0] op1,
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op2,
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op3;
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wire [7:0] op2_direct;
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|
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/////////////////////////////
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//
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// pc
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|
//
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/////////////////////////////
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input [2:0] pc_wr_sel;
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input [2:0] pc_wr_sel;
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|
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input pc_wr;
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input pc_wr;
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output [15:0] pc;
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output [15:0] pc;
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|
|
|
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reg [15:0] pc;
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reg [15:0] pc;
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//
|
//
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//pc program counter register, save current value
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//pc program counter register, save current value
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reg [15:0] pc_buf;
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reg [15:0] pc_buf;
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wire [15:0] alu;
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wire [15:0] alu;
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//
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// wr_lo write low: used in reti instruction, write only low byte of pc
|
reg int_buff,
|
// ini_buff interrupt buffer: used to prevent interrupting in the middle of executin instructions
|
int_buff1; // interrupt buffer: used to prevent interrupting in the middle of executin instructions
|
reg int_buff, int_buff1;
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|
|
|
|
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//
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//
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//
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//
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////////////////////////////
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////////////////////////////
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reg istb_t, imem_wait, dstb_o, dwe_o;
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reg istb_t,
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//reg [3:0] mem_act_r;
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imem_wait,
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dstb_o,
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dwe_o;
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reg [7:0] ddat_o;
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reg [7:0] ddat_o;
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reg [15:0] iadr_t, dadr_ot;
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reg [15:0] iadr_t,
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dadr_ot;
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reg dmem_wait;
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reg dmem_wait;
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wire pc_wait;
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wire pc_wait;
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wire [1:0] bank;
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wire [1:0] bank;
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//wire pis_l;
|
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wire [15:0] iadr_ot;
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wire [7:0] isr_call;
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wire [7:0] isr_call;
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|
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reg [1:0] op_length;
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reg [2:0] op_pos;
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wire inc_pc;
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reg pc_wr_r;
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|
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wire [15:0] pc_out;
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|
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reg [31:0] idat_cur,
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idat_old;
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|
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reg inc_pc_r,
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pc_wr_r2;
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reg [7:0] cdata;
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reg cdone;
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|
|
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assign bank = rn[4:3];
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assign bank = rn[4:3];
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assign imm = op2_out;
|
assign imm = op2_out;
|
assign imm2 = op3_out;
|
assign imm2 = op3_out;
|
assign alu = {des2, des_acc};
|
assign alu = {des2, des_acc};
|
assign ea_rom_sel = ea && ea_int;
|
assign ea_rom_sel = ea && ea_int;
|
assign wr_o = wr_i;
|
assign wr_o = wr_i;
|
assign wr_bit_o = wr_bit_i;
|
assign wr_bit_o = wr_bit_i;
|
|
|
assign mem_wait = dmem_wait || imem_wait;
|
//assign mem_wait = dmem_wait || imem_wait || pc_wr_r;
|
|
assign mem_wait = dmem_wait || imem_wait || pc_wr_r2;
|
|
//assign mem_wait = dmem_wait || imem_wait;
|
assign istb_o = (istb || (istb_t & !iack_i)) && !dstb_o && !ea_rom_sel;
|
assign istb_o = (istb || (istb_t & !iack_i)) && !dstb_o && !ea_rom_sel;
|
|
|
assign pc_wait = rd && (ea_rom_sel || (!istb_t && iack_i));
|
assign pc_wait = rd && (ea_rom_sel || (!istb_t && iack_i));
|
|
|
assign wr_dat = des1;
|
assign wr_dat = des1;
|
| Line 315... |
Line 432... |
/////////////////////////////
|
/////////////////////////////
|
//
|
//
|
// output address is alu destination
|
// output address is alu destination
|
// (instructions MOVC)
|
// (instructions MOVC)
|
|
|
assign iadr_ot = (istb_t & !iack_i) ? iadr_t : pc;
|
//assign iadr_o = (istb_t & !iack_i) ? iadr_t : pc_out;
|
assign iadr_o = iadr_ot;
|
assign iadr_o = (istb_t) ? iadr_t : pc_out;
|
|
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
iadr_t <= #1 23'h0;
|
iadr_t <= #1 23'h0;
|
istb_t <= #1 1'b0;
|
istb_t <= #1 1'b0;
|
imem_wait <= #1 1'b0;
|
imem_wait <= #1 1'b0;
|
idat_ir <= #1 24'h0;
|
idat_ir <= #1 24'h0;
|
end else if (iack_i) begin
|
|
istb_t <= #1 1'b0;
|
|
imem_wait <= #1 1'b0;
|
|
idat_ir <= #1 idat_i [23:0];
|
|
end else if (ea_rom_sel && imem_wait) begin
|
|
imem_wait <= #1 1'b0;
|
|
end else if (ea_rom_sel && !imem_wait && istb_t) begin
|
|
istb_t <= #1 1'b0;
|
|
end else if (mem_act==`OC8051_MAS_CODE) begin
|
end else if (mem_act==`OC8051_MAS_CODE) begin
|
iadr_t <= #1 alu;
|
iadr_t <= #1 alu;
|
istb_t <= #1 1'b1;
|
istb_t <= #1 1'b1;
|
imem_wait <= #1 1'b1;
|
imem_wait <= #1 1'b1;
|
|
end else if (ea_rom_sel && imem_wait) begin
|
|
imem_wait <= #1 1'b0;
|
|
end else if (!imem_wait && istb_t) begin
|
|
istb_t <= #1 1'b0;
|
|
end else if (iack_i) begin
|
|
imem_wait <= #1 1'b0;
|
|
idat_ir <= #1 idat_i [23:0];
|
end
|
end
|
end
|
end
|
|
|
/////////////////////////////
|
/////////////////////////////
|
//
|
//
|
| Line 402... |
Line 518... |
// op_select
|
// op_select
|
//
|
//
|
/////////////////////////////
|
/////////////////////////////
|
|
|
|
|
assign op1 = ea_rom_sel ? op1_i: op1_xt;
|
|
assign op2 = ea_rom_sel ? op2_i: op2_xt;
|
|
assign op3 = ea_rom_sel ? op3_i: op3_xt;
|
|
|
|
|
always @(posedge clk or posedge rst)
|
|
begin
|
|
if (rst) begin
|
|
idat_cur <= #1 32'h0;
|
|
idat_old <= #1 32'h0;
|
|
end else if ((iack_i | ea_rom_sel) & (inc_pc | pc_wr_r2)) begin
|
|
idat_cur <= #1 ea_rom_sel ? idat_onchip : idat_i;
|
|
idat_old <= #1 idat_cur;
|
|
end
|
|
|
always @(dack_ir or ddat_ir or op1_o or iram_out)
|
end
|
|
|
|
always @(posedge clk or posedge rst)
|
|
begin
|
|
if (rst) begin
|
|
cdata <= #1 8'h00;
|
|
cdone <= #1 1'b0;
|
|
end else if (istb_t) begin
|
|
cdata <= #1 ea_rom_sel ? idat_onchip[7:0] : idat_i[7:0];
|
|
cdone <= #1 1'b1;
|
|
end else begin
|
|
cdone <= #1 1'b0;
|
|
end
|
|
end
|
|
|
|
always @(op_pos or idat_cur or idat_old)
|
|
begin
|
|
case (op_pos)
|
|
3'b000: begin
|
|
op1 = idat_old[7:0] ;
|
|
op2 = idat_old[15:8] ;
|
|
op3 = idat_old[23:16];
|
|
end
|
|
3'b001: begin
|
|
op1 = idat_old[15:8] ;
|
|
op2 = idat_old[23:16];
|
|
op3 = idat_old[31:24];
|
|
end
|
|
3'b010: begin
|
|
op1 = idat_old[23:16];
|
|
op2 = idat_old[31:24];
|
|
op3 = idat_cur[7:0] ;
|
|
end
|
|
3'b011: begin
|
|
op1 = idat_old[31:24];
|
|
op2 = idat_cur[7:0] ;
|
|
op3 = idat_cur[15:8] ;
|
|
end
|
|
3'b100: begin
|
|
op1 = idat_cur[7:0] ;
|
|
op2 = idat_cur[15:8] ;
|
|
op3 = idat_cur[23:16];
|
|
end
|
|
default: begin
|
|
op1 = idat_cur[15:8] ;
|
|
op2 = idat_cur[23:16];
|
|
op3 = idat_cur[31:24];
|
|
end
|
|
endcase
|
|
end
|
|
|
|
/*assign op1 = ea_rom_sel ? idat_onchip[7:0] : op1_xt;
|
|
assign op2 = ea_rom_sel ? idat_onchip[15:8] : op2_xt;
|
|
assign op3 = ea_rom_sel ? idat_onchip[23:16] : op3_xt;*/
|
|
|
|
|
|
always @(dack_ir or ddat_ir or op1_o or iram_out or cdone or cdata)
|
if (dack_ir)
|
if (dack_ir)
|
op1_out = ddat_ir;
|
op1_out = ddat_ir;
|
|
else if (cdone)
|
|
op1_out = cdata;
|
else
|
else
|
op1_out = op1_o;
|
op1_out = op1_o;
|
|
|
assign op3_out = (rd) ? op3_o : op3_buff;
|
assign op3_out = (rd) ? op3_o : op3_buff;
|
assign op2_out = (rd) ? op2_o : op2_buff;
|
assign op2_out = (rd) ? op2_o : op2_buff;
|
| Line 453... |
Line 633... |
|
|
//
|
//
|
//in case of reti
|
//in case of reti
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst) reti <= #1 1'b0;
|
if (rst) reti <= #1 1'b0;
|
else if ((op1_o==`OC8051_RETI) & rd) reti <= #1 1'b1;
|
else if ((op1_o==`OC8051_RETI) & rd & !mem_wait) reti <= #1 1'b1;
|
else reti <= #1 1'b0;
|
else reti <= #1 1'b0;
|
|
|
//
|
//
|
// remember inputs
|
// remember inputs
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
| Line 469... |
Line 649... |
op2_buff <= #1 op2_o;
|
op2_buff <= #1 op2_o;
|
op3_buff <= #1 op3_o;
|
op3_buff <= #1 op3_o;
|
end
|
end
|
end
|
end
|
|
|
|
/////////////////////////////
|
|
//
|
|
// pc
|
|
//
|
|
/////////////////////////////
|
|
|
|
always @(op1_out)
|
|
begin
|
|
casex (op1_out)
|
|
`OC8051_ACALL : op_length = 2'h2;
|
|
`OC8051_AJMP : op_length = 2'h2;
|
|
|
|
//op_code [7:3]
|
|
`OC8051_CJNE_R : op_length = 2'h3;
|
|
`OC8051_DJNZ_R : op_length = 2'h2;
|
|
`OC8051_MOV_DR : op_length = 2'h2;
|
|
`OC8051_MOV_CR : op_length = 2'h2;
|
|
`OC8051_MOV_RD : op_length = 2'h2;
|
|
|
|
//op_code [7:1]
|
|
`OC8051_CJNE_I : op_length = 2'h3;
|
|
`OC8051_MOV_ID : op_length = 2'h2;
|
|
`OC8051_MOV_DI : op_length = 2'h2;
|
|
`OC8051_MOV_CI : op_length = 2'h2;
|
|
|
|
//op_code [7:0]
|
|
`OC8051_ADD_D : op_length = 2'h2;
|
|
`OC8051_ADD_C : op_length = 2'h2;
|
|
`OC8051_ADDC_D : op_length = 2'h2;
|
|
`OC8051_ADDC_C : op_length = 2'h2;
|
|
`OC8051_ANL_D : op_length = 2'h2;
|
|
`OC8051_ANL_C : op_length = 2'h2;
|
|
`OC8051_ANL_DD : op_length = 2'h2;
|
|
`OC8051_ANL_DC : op_length = 2'h3;
|
|
`OC8051_ANL_B : op_length = 2'h2;
|
|
`OC8051_ANL_NB : op_length = 2'h2;
|
|
`OC8051_CJNE_D : op_length = 2'h3;
|
|
`OC8051_CJNE_C : op_length = 2'h3;
|
|
`OC8051_CLR_B : op_length = 2'h2;
|
|
`OC8051_CPL_B : op_length = 2'h2;
|
|
`OC8051_DEC_D : op_length = 2'h2;
|
|
`OC8051_DJNZ_D : op_length = 2'h3;
|
|
`OC8051_INC_D : op_length = 2'h2;
|
|
`OC8051_JB : op_length = 2'h3;
|
|
`OC8051_JBC : op_length = 2'h3;
|
|
`OC8051_JC : op_length = 2'h2;
|
|
`OC8051_JNB : op_length = 2'h3;
|
|
`OC8051_JNC : op_length = 2'h2;
|
|
`OC8051_JNZ : op_length = 2'h2;
|
|
`OC8051_JZ : op_length = 2'h2;
|
|
`OC8051_LCALL : op_length = 2'h3;
|
|
`OC8051_LJMP : op_length = 2'h3;
|
|
`OC8051_MOV_D : op_length = 2'h2;
|
|
`OC8051_MOV_C : op_length = 2'h2;
|
|
`OC8051_MOV_DA : op_length = 2'h2;
|
|
`OC8051_MOV_DD : op_length = 2'h3;
|
|
`OC8051_MOV_CD : op_length = 2'h3;
|
|
`OC8051_MOV_BC : op_length = 2'h2;
|
|
`OC8051_MOV_CB : op_length = 2'h2;
|
|
`OC8051_MOV_DP : op_length = 2'h3;
|
|
`OC8051_ORL_D : op_length = 2'h2;
|
|
`OC8051_ORL_C : op_length = 2'h2;
|
|
`OC8051_ORL_AD : op_length = 2'h2;
|
|
`OC8051_ORL_CD : op_length = 2'h3;
|
|
`OC8051_ORL_B : op_length = 2'h2;
|
|
`OC8051_ORL_NB : op_length = 2'h2;
|
|
`OC8051_POP : op_length = 2'h2;
|
|
`OC8051_PUSH : op_length = 2'h2;
|
|
`OC8051_SETB_B : op_length = 2'h2;
|
|
`OC8051_SJMP : op_length = 2'h2;
|
|
`OC8051_SUBB_D : op_length = 2'h2;
|
|
`OC8051_SUBB_C : op_length = 2'h2;
|
|
`OC8051_XCH_D : op_length = 2'h2;
|
|
`OC8051_XRL_D : op_length = 2'h2;
|
|
`OC8051_XRL_C : op_length = 2'h2;
|
|
`OC8051_XRL_AD : op_length = 2'h2;
|
|
`OC8051_XRL_CD : op_length = 2'h3;
|
|
default: op_length = 2'h1;
|
|
endcase
|
|
end
|
|
|
|
/*
|
|
always @(posedge clk or posedge rst)
|
|
begin
|
|
if (rst) begin
|
|
op_length = 2'h2;
|
|
// end else if (pc_wait) begin
|
|
end else begin
|
|
casex (op1_out)
|
|
`OC8051_ACALL : op_length <= #1 2'h2;
|
|
`OC8051_AJMP : op_length <= #1 2'h2;
|
|
|
|
//op_code [7:3]
|
|
`OC8051_CJNE_R : op_length <= #1 2'h3;
|
|
`OC8051_DJNZ_R : op_length <= #1 2'h2;
|
|
`OC8051_MOV_DR : op_length <= #1 2'h2;
|
|
`OC8051_MOV_CR : op_length <= #1 2'h2;
|
|
`OC8051_MOV_RD : op_length <= #1 2'h2;
|
|
|
|
//op_code [7:1]
|
|
`OC8051_CJNE_I : op_length <= #1 2'h3;
|
|
`OC8051_MOV_ID : op_length <= #1 2'h2;
|
|
`OC8051_MOV_DI : op_length <= #1 2'h2;
|
|
`OC8051_MOV_CI : op_length <= #1 2'h2;
|
|
|
|
//op_code [7:0]
|
|
`OC8051_ADD_D : op_length <= #1 2'h2;
|
|
`OC8051_ADD_C : op_length <= #1 2'h2;
|
|
`OC8051_ADDC_D : op_length <= #1 2'h2;
|
|
`OC8051_ADDC_C : op_length <= #1 2'h2;
|
|
`OC8051_ANL_D : op_length <= #1 2'h2;
|
|
`OC8051_ANL_C : op_length <= #1 2'h2;
|
|
`OC8051_ANL_DD : op_length <= #1 2'h2;
|
|
`OC8051_ANL_DC : op_length <= #1 2'h3;
|
|
`OC8051_ANL_B : op_length <= #1 2'h2;
|
|
`OC8051_ANL_NB : op_length <= #1 2'h2;
|
|
`OC8051_CJNE_D : op_length <= #1 2'h3;
|
|
`OC8051_CJNE_C : op_length <= #1 2'h3;
|
|
`OC8051_CLR_B : op_length <= #1 2'h2;
|
|
`OC8051_CPL_B : op_length <= #1 2'h2;
|
|
`OC8051_DEC_D : op_length <= #1 2'h2;
|
|
`OC8051_DJNZ_D : op_length <= #1 2'h3;
|
|
`OC8051_INC_D : op_length <= #1 2'h2;
|
|
`OC8051_JB : op_length <= #1 2'h3;
|
|
`OC8051_JBC : op_length <= #1 2'h3;
|
|
`OC8051_JC : op_length <= #1 2'h2;
|
|
`OC8051_JNB : op_length <= #1 2'h3;
|
|
`OC8051_JNC : op_length <= #1 2'h2;
|
|
`OC8051_JNZ : op_length <= #1 2'h2;
|
|
`OC8051_JZ : op_length <= #1 2'h2;
|
|
`OC8051_LCALL : op_length <= #1 2'h3;
|
|
`OC8051_LJMP : op_length <= #1 2'h3;
|
|
`OC8051_MOV_D : op_length <= #1 2'h2;
|
|
`OC8051_MOV_C : op_length <= #1 2'h2;
|
|
`OC8051_MOV_DA : op_length <= #1 2'h2;
|
|
`OC8051_MOV_DD : op_length <= #1 2'h3;
|
|
`OC8051_MOV_CD : op_length <= #1 2'h3;
|
|
`OC8051_MOV_BC : op_length <= #1 2'h2;
|
|
`OC8051_MOV_CB : op_length <= #1 2'h2;
|
|
`OC8051_MOV_DP : op_length <= #1 2'h3;
|
|
`OC8051_ORL_D : op_length <= #1 2'h2;
|
|
`OC8051_ORL_C : op_length <= #1 2'h2;
|
|
`OC8051_ORL_AD : op_length <= #1 2'h2;
|
|
`OC8051_ORL_CD : op_length <= #1 2'h3;
|
|
`OC8051_ORL_B : op_length <= #1 2'h2;
|
|
`OC8051_ORL_NB : op_length <= #1 2'h2;
|
|
`OC8051_POP : op_length <= #1 2'h2;
|
|
`OC8051_PUSH : op_length <= #1 2'h2;
|
|
`OC8051_SETB_B : op_length <= #1 2'h2;
|
|
`OC8051_SJMP : op_length <= #1 2'h2;
|
|
`OC8051_SUBB_D : op_length <= #1 2'h2;
|
|
`OC8051_SUBB_C : op_length <= #1 2'h2;
|
|
`OC8051_XCH_D : op_length <= #1 2'h2;
|
|
`OC8051_XRL_D : op_length <= #1 2'h2;
|
|
`OC8051_XRL_C : op_length <= #1 2'h2;
|
|
`OC8051_XRL_AD : op_length <= #1 2'h2;
|
|
`OC8051_XRL_CD : op_length <= #1 2'h3;
|
|
default: op_length <= #1 2'h1;
|
|
endcase
|
|
//
|
|
//in case of instructions that use more than one clock hold current pc
|
|
// end else begin
|
|
// pc= pc_buf;
|
|
end
|
|
end
|
|
*/
|
|
|
|
assign inc_pc = ((op_pos[2] | (&op_pos[1:0])) & rd) | pc_wr_r2;
|
|
|
|
always @(posedge rst or posedge clk)
|
|
begin
|
|
if (rst) begin
|
|
op_pos <= #1 3'h0;
|
|
end else if (pc_wr_r2) begin
|
|
op_pos <= #1 3'h4;// - op_length;////****??????????
|
|
/* end else if (inc_pc & rd) begin
|
|
op_pos[2] <= #1 op_pos[2] & !op_pos[1] & op_pos[0] & (&op_length);
|
|
op_pos[1:0] <= #1 op_pos[1:0] + op_length;
|
|
// op_pos <= #1 {1'b0, op_pos[1:0]} + {1'b0, op_length};
|
|
end else if (rd) begin
|
|
op_pos <= #1 op_pos + {1'b0, op_length};
|
|
end*/
|
|
end else if (inc_pc & rd) begin
|
|
op_pos[2] <= #1 op_pos[2] & !op_pos[1] & op_pos[0] & (&op_length);
|
|
op_pos[1:0] <= #1 op_pos[1:0] + op_length;
|
|
// op_pos <= #1 {1'b0, op_pos[1:0]} + {1'b0, op_length};
|
|
// end else if (istb & rd) begin
|
|
end else if (rd) begin
|
|
op_pos <= #1 op_pos + {1'b0, op_length};
|
|
end
|
|
end
|
|
|
//
|
//
|
// remember interrupt
|
// remember interrupt
|
// we don't want to interrupt instruction in the middle of execution
|
// we don't want to interrupt instruction in the middle of execution
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst) begin
|
if (rst) begin
|
int_ack_t <= #1 1'b0;
|
int_ack_t <= #1 1'b0;
|
int_vec_buff <= #1 8'h00;
|
int_vec_buff <= #1 8'h00;
|
end else if (intr) begin
|
end else if (intr) begin
|
int_ack_t <= #1 1'b1;
|
int_ack_t <= #1 1'b1;
|
int_vec_buff <= #1 int_v;
|
int_vec_buff <= #1 int_v;
|
end else if (rd && (ea_rom_sel || iack_i)) int_ack_t <= #1 1'b0;
|
end else if (rd && (ea_rom_sel || iack_i) && !pc_wr_r2) int_ack_t <= #1 1'b0;
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst) int_ack_buff <= #1 1'b0;
|
if (rst) int_ack_buff <= #1 1'b0;
|
else int_ack_buff <= #1 int_ack_t;
|
else int_ack_buff <= #1 int_ack_t;
|
|
|
| Line 494... |
Line 866... |
int_ack <= #1 1'b1;
|
int_ack <= #1 1'b1;
|
else int_ack <= #1 1'b0;
|
else int_ack <= #1 1'b0;
|
end
|
end
|
|
|
|
|
/////////////////////////////
|
|
//
|
|
// pc
|
|
//
|
|
/////////////////////////////
|
|
|
|
always @(pc_buf or op1_out or pc_wait or int_buff or int_buff1 or ea_rom_sel or iack_i)
|
|
begin
|
|
if (int_buff || int_buff1) begin
|
|
//
|
|
//in case of interrupt hold valut, to be written to stack
|
|
pc= pc_buf;
|
|
// end else if (pis_l) begin
|
|
// pc = {pc_buf[22:8], alu[7:0]};
|
|
end else if (pc_wait) begin
|
|
casex (op1_out)
|
|
`OC8051_ACALL : pc= pc_buf + 16'h2;
|
|
`OC8051_AJMP : pc= pc_buf + 16'h2;
|
|
|
|
//op_code [7:3]
|
|
`OC8051_CJNE_R : pc= pc_buf + 16'h3;
|
|
`OC8051_DJNZ_R : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_DR : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_CR : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_RD : pc= pc_buf + 16'h2;
|
|
|
|
//op_code [7:1]
|
|
`OC8051_CJNE_I : pc= pc_buf + 16'h3;
|
|
`OC8051_MOV_ID : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_DI : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_CI : pc= pc_buf + 16'h2;
|
|
|
|
//op_code [7:0]
|
|
`OC8051_ADD_D : pc= pc_buf + 16'h2;
|
|
`OC8051_ADD_C : pc= pc_buf + 16'h2;
|
|
`OC8051_ADDC_D : pc= pc_buf + 16'h2;
|
|
`OC8051_ADDC_C : pc= pc_buf + 16'h2;
|
|
`OC8051_ANL_D : pc= pc_buf + 16'h2;
|
|
`OC8051_ANL_C : pc= pc_buf + 16'h2;
|
|
`OC8051_ANL_DD : pc= pc_buf + 16'h2;
|
|
`OC8051_ANL_DC : pc= pc_buf + 16'h3;
|
|
`OC8051_ANL_B : pc= pc_buf + 16'h2;
|
|
`OC8051_ANL_NB : pc= pc_buf + 16'h2;
|
|
`OC8051_CJNE_D : pc= pc_buf + 16'h3;
|
|
`OC8051_CJNE_C : pc= pc_buf + 16'h3;
|
|
`OC8051_CLR_B : pc= pc_buf + 16'h2;
|
|
`OC8051_CPL_B : pc= pc_buf + 16'h2;
|
|
`OC8051_DEC_D : pc= pc_buf + 16'h2;
|
|
`OC8051_DJNZ_D : pc= pc_buf + 16'h3;
|
|
`OC8051_INC_D : pc= pc_buf + 16'h2;
|
|
`OC8051_JB : pc= pc_buf + 16'h3;
|
|
`OC8051_JBC : pc= pc_buf + 16'h3;
|
|
`OC8051_JC : pc= pc_buf + 16'h2;
|
|
`OC8051_JNB : pc= pc_buf + 16'h3;
|
|
`OC8051_JNC : pc= pc_buf + 16'h2;
|
|
`OC8051_JNZ : pc= pc_buf + 16'h2;
|
|
`OC8051_JZ : pc= pc_buf + 16'h2;
|
|
`OC8051_LCALL : pc= pc_buf + 16'h3;
|
|
`OC8051_LJMP : pc= pc_buf + 16'h3;
|
|
`OC8051_MOV_D : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_C : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_DA : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_DD : pc= pc_buf + 16'h3;
|
|
`OC8051_MOV_CD : pc= pc_buf + 16'h3;
|
|
`OC8051_MOV_BC : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_CB : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_DP : pc= pc_buf + 16'h3;
|
|
`OC8051_ORL_D : pc= pc_buf + 16'h2;
|
|
`OC8051_ORL_C : pc= pc_buf + 16'h2;
|
|
`OC8051_ORL_AD : pc= pc_buf + 16'h2;
|
|
`OC8051_ORL_CD : pc= pc_buf + 16'h3;
|
|
`OC8051_ORL_B : pc= pc_buf + 16'h2;
|
|
`OC8051_ORL_NB : pc= pc_buf + 16'h2;
|
|
`OC8051_POP : pc= pc_buf + 16'h2;
|
|
`OC8051_PUSH : pc= pc_buf + 16'h2;
|
|
`OC8051_SETB_B : pc= pc_buf + 16'h2;
|
|
`OC8051_SJMP : pc= pc_buf + 16'h2;
|
|
`OC8051_SUBB_D : pc= pc_buf + 16'h2;
|
|
`OC8051_SUBB_C : pc= pc_buf + 16'h2;
|
|
`OC8051_XCH_D : pc= pc_buf + 16'h2;
|
|
`OC8051_XRL_D : pc= pc_buf + 16'h2;
|
|
`OC8051_XRL_C : pc= pc_buf + 16'h2;
|
|
`OC8051_XRL_AD : pc= pc_buf + 16'h2;
|
|
`OC8051_XRL_CD : pc= pc_buf + 16'h3;
|
|
default: pc= pc_buf + 16'h1;
|
|
endcase
|
|
//
|
|
//in case of instructions that use more than one clock hold current pc
|
|
end else begin
|
|
pc= pc_buf;
|
|
end
|
|
end
|
|
|
|
|
|
//
|
//
|
//interrupt buffer
|
//interrupt buffer
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst) begin
|
if (rst) begin
|
int_buff1 <= #1 1'b0;
|
int_buff1 <= #1 1'b0;
|
| Line 619... |
Line 897... |
{pcs_cy, pcs_result[7:0]} = {1'b0, pc[7:0]} + {1'b0, pcs_source};
|
{pcs_cy, pcs_result[7:0]} = {1'b0, pc[7:0]} + {1'b0, pcs_source};
|
pcs_result[15:8] = pc[15:8] - {7'h0, !pcs_cy};
|
pcs_result[15:8] = pc[15:8] - {7'h0, !pcs_cy};
|
end else pcs_result = pc + {8'h00, pcs_source};
|
end else pcs_result = pc + {8'h00, pcs_source};
|
end
|
end
|
|
|
|
//assign pc = pc_buf - {13'h0, op_pos[2] | inc_pc_r, op_pos[1:0]}; ////******???
|
|
//assign pc = pc_buf - 16'h8 + {13'h0, op_pos}; ////******???
|
|
//assign pc = pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length};
|
|
|
|
always @(posedge clk or posedge rst)
|
|
begin
|
|
if (rst)
|
|
pc <= #1 16'h0;
|
|
else if (pc_wr_r2)
|
|
pc <= #1 pc_buf;
|
|
else if (rd & !int_ack_t)
|
|
pc <= #1 pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length};
|
|
end
|
|
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
pc_buf <= #1 `OC8051_RST_PC;
|
pc_buf <= #1 `OC8051_RST_PC;
|
end else begin
|
end else if (pc_wr) begin
|
if (pc_wr) begin
|
|
//
|
//
|
//case of writing new value to pc (jupms)
|
//case of writing new value to pc (jupms)
|
case (pc_wr_sel)
|
case (pc_wr_sel)
|
`OC8051_PIS_ALU: pc_buf <= #1 alu;
|
`OC8051_PIS_ALU: pc_buf <= #1 alu;
|
`OC8051_PIS_AL: pc_buf[7:0] <= #1 alu[7:0];
|
`OC8051_PIS_AL: pc_buf[7:0] <= #1 alu[7:0];
|
| Line 637... |
Line 928... |
`OC8051_PIS_I11: pc_buf[10:0] <= #1 {op1_out[7:5], op2_out};
|
`OC8051_PIS_I11: pc_buf[10:0] <= #1 {op1_out[7:5], op2_out};
|
`OC8051_PIS_I16: pc_buf <= #1 {op2_out, op3_out};
|
`OC8051_PIS_I16: pc_buf <= #1 {op2_out, op3_out};
|
`OC8051_PIS_SO1: pc_buf <= #1 pcs_result;
|
`OC8051_PIS_SO1: pc_buf <= #1 pcs_result;
|
`OC8051_PIS_SO2: pc_buf <= #1 pcs_result;
|
`OC8051_PIS_SO2: pc_buf <= #1 pcs_result;
|
endcase
|
endcase
|
end else
|
// end else if (inc_pc) begin
|
|
end else begin
|
//
|
//
|
//or just remember current
|
//or just remember current
|
pc_buf <= #1 pc;
|
pc_buf <= #1 pc_out;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
assign pc_out = inc_pc ? pc_buf + 16'h4
|
|
: pc_buf ;
|
|
|
|
|
|
|
|
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
ddat_ir <= #1 8'h00;
|
ddat_ir <= #1 8'h00;
|
else if (dack_i)
|
else if (dack_i)
|
ddat_ir <= #1 ddat_i;
|
ddat_ir <= #1 ddat_i;
|
|
|
|
/*
|
|
|
|
always @(pc_buf or op1_out or pc_wait or int_buff or int_buff1 or ea_rom_sel or iack_i)
|
|
begin
|
|
if (int_buff || int_buff1) begin
|
|
//
|
|
//in case of interrupt hold valut, to be written to stack
|
|
pc= pc_buf;
|
|
// end else if (pis_l) begin
|
|
// pc = {pc_buf[22:8], alu[7:0]};
|
|
end else if (pc_wait) begin
|
|
casex (op1_out)
|
|
`OC8051_ACALL : pc= pc_buf + 16'h2;
|
|
`OC8051_AJMP : pc= pc_buf + 16'h2;
|
|
|
|
//op_code [7:3]
|
|
`OC8051_CJNE_R : pc= pc_buf + 16'h3;
|
|
`OC8051_DJNZ_R : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_DR : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_CR : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_RD : pc= pc_buf + 16'h2;
|
|
|
|
//op_code [7:1]
|
|
`OC8051_CJNE_I : pc= pc_buf + 16'h3;
|
|
`OC8051_MOV_ID : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_DI : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_CI : pc= pc_buf + 16'h2;
|
|
|
|
//op_code [7:0]
|
|
`OC8051_ADD_D : pc= pc_buf + 16'h2;
|
|
`OC8051_ADD_C : pc= pc_buf + 16'h2;
|
|
`OC8051_ADDC_D : pc= pc_buf + 16'h2;
|
|
`OC8051_ADDC_C : pc= pc_buf + 16'h2;
|
|
`OC8051_ANL_D : pc= pc_buf + 16'h2;
|
|
`OC8051_ANL_C : pc= pc_buf + 16'h2;
|
|
`OC8051_ANL_DD : pc= pc_buf + 16'h2;
|
|
`OC8051_ANL_DC : pc= pc_buf + 16'h3;
|
|
`OC8051_ANL_B : pc= pc_buf + 16'h2;
|
|
`OC8051_ANL_NB : pc= pc_buf + 16'h2;
|
|
`OC8051_CJNE_D : pc= pc_buf + 16'h3;
|
|
`OC8051_CJNE_C : pc= pc_buf + 16'h3;
|
|
`OC8051_CLR_B : pc= pc_buf + 16'h2;
|
|
`OC8051_CPL_B : pc= pc_buf + 16'h2;
|
|
`OC8051_DEC_D : pc= pc_buf + 16'h2;
|
|
`OC8051_DJNZ_D : pc= pc_buf + 16'h3;
|
|
`OC8051_INC_D : pc= pc_buf + 16'h2;
|
|
`OC8051_JB : pc= pc_buf + 16'h3;
|
|
`OC8051_JBC : pc= pc_buf + 16'h3;
|
|
`OC8051_JC : pc= pc_buf + 16'h2;
|
|
`OC8051_JNB : pc= pc_buf + 16'h3;
|
|
`OC8051_JNC : pc= pc_buf + 16'h2;
|
|
`OC8051_JNZ : pc= pc_buf + 16'h2;
|
|
`OC8051_JZ : pc= pc_buf + 16'h2;
|
|
`OC8051_LCALL : pc= pc_buf + 16'h3;
|
|
`OC8051_LJMP : pc= pc_buf + 16'h3;
|
|
`OC8051_MOV_D : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_C : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_DA : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_DD : pc= pc_buf + 16'h3;
|
|
`OC8051_MOV_CD : pc= pc_buf + 16'h3;
|
|
`OC8051_MOV_BC : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_CB : pc= pc_buf + 16'h2;
|
|
`OC8051_MOV_DP : pc= pc_buf + 16'h3;
|
|
`OC8051_ORL_D : pc= pc_buf + 16'h2;
|
|
`OC8051_ORL_C : pc= pc_buf + 16'h2;
|
|
`OC8051_ORL_AD : pc= pc_buf + 16'h2;
|
|
`OC8051_ORL_CD : pc= pc_buf + 16'h3;
|
|
`OC8051_ORL_B : pc= pc_buf + 16'h2;
|
|
`OC8051_ORL_NB : pc= pc_buf + 16'h2;
|
|
`OC8051_POP : pc= pc_buf + 16'h2;
|
|
`OC8051_PUSH : pc= pc_buf + 16'h2;
|
|
`OC8051_SETB_B : pc= pc_buf + 16'h2;
|
|
`OC8051_SJMP : pc= pc_buf + 16'h2;
|
|
`OC8051_SUBB_D : pc= pc_buf + 16'h2;
|
|
`OC8051_SUBB_C : pc= pc_buf + 16'h2;
|
|
`OC8051_XCH_D : pc= pc_buf + 16'h2;
|
|
`OC8051_XRL_D : pc= pc_buf + 16'h2;
|
|
`OC8051_XRL_C : pc= pc_buf + 16'h2;
|
|
`OC8051_XRL_AD : pc= pc_buf + 16'h2;
|
|
`OC8051_XRL_CD : pc= pc_buf + 16'h3;
|
|
default: pc= pc_buf + 16'h1;
|
|
endcase
|
|
//
|
|
//in case of instructions that use more than one clock hold current pc
|
|
end else begin
|
|
pc= pc_buf;
|
|
end
|
|
end
|
|
|
|
|
|
//
|
|
//interrupt buffer
|
|
always @(posedge clk or posedge rst)
|
|
if (rst) begin
|
|
int_buff1 <= #1 1'b0;
|
|
end else begin
|
|
int_buff1 <= #1 int_buff;
|
|
end
|
|
|
|
always @(posedge clk or posedge rst)
|
|
if (rst) begin
|
|
int_buff <= #1 1'b0;
|
|
end else if (intr) begin
|
|
int_buff <= #1 1'b1;
|
|
end else if (pc_wait)
|
|
int_buff <= #1 1'b0;
|
|
|
|
wire [7:0] pcs_source;
|
|
reg [15:0] pcs_result;
|
|
reg pcs_cy;
|
|
|
|
assign pcs_source = pc_wr_sel[0] ? op3_out : op2_out;
|
|
|
|
always @(pcs_source or pc or pcs_cy)
|
|
begin
|
|
if (pcs_source[7]) begin
|
|
{pcs_cy, pcs_result[7:0]} = {1'b0, pc[7:0]} + {1'b0, pcs_source};
|
|
pcs_result[15:8] = pc[15:8] - {7'h0, !pcs_cy};
|
|
end else pcs_result = pc + {8'h00, pcs_source};
|
|
end
|
|
|
|
|
|
always @(posedge clk or posedge rst)
|
|
begin
|
|
if (rst) begin
|
|
pc_buf <= #1 `OC8051_RST_PC;
|
|
end else begin
|
|
if (pc_wr) begin
|
|
//
|
|
//case of writing new value to pc (jupms)
|
|
case (pc_wr_sel)
|
|
`OC8051_PIS_ALU: pc_buf <= #1 alu;
|
|
`OC8051_PIS_AL: pc_buf[7:0] <= #1 alu[7:0];
|
|
`OC8051_PIS_AH: pc_buf[15:8] <= #1 alu[7:0];
|
|
`OC8051_PIS_I11: pc_buf[10:0] <= #1 {op1_out[7:5], op2_out};
|
|
`OC8051_PIS_I16: pc_buf <= #1 {op2_out, op3_out};
|
|
`OC8051_PIS_SO1: pc_buf <= #1 pcs_result;
|
|
`OC8051_PIS_SO2: pc_buf <= #1 pcs_result;
|
|
endcase
|
|
end else
|
|
//
|
|
//or just remember current
|
|
pc_buf <= #1 pc;
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge clk or posedge rst)
|
|
if (rst)
|
|
ddat_ir <= #1 8'h00;
|
|
else if (dack_i)
|
|
ddat_ir <= #1 ddat_i;
|
|
*/
|
|
|
////////////////////////
|
////////////////////////
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst) begin
|
if (rst) begin
|
rn_r <= #1 5'd0;
|
rn_r <= #1 5'd0;
|
ri_r <= #1 8'h00;
|
ri_r <= #1 8'h00;
|
| Line 662... |
Line 1115... |
imm2_r <= #1 8'h00;
|
imm2_r <= #1 8'h00;
|
rd_addr_r <= #1 1'b0;
|
rd_addr_r <= #1 1'b0;
|
op1_r <= #1 8'h0;
|
op1_r <= #1 8'h0;
|
dack_ir <= #1 1'b0;
|
dack_ir <= #1 1'b0;
|
sp_r <= #1 1'b0;
|
sp_r <= #1 1'b0;
|
|
pc_wr_r <= #1 1'b0;
|
|
pc_wr_r2 <= #1 1'b0;
|
end else begin
|
end else begin
|
rn_r <= #1 rn;
|
rn_r <= #1 rn;
|
ri_r <= #1 ri;
|
ri_r <= #1 ri;
|
imm_r <= #1 imm;
|
imm_r <= #1 imm;
|
imm2_r <= #1 imm2;
|
imm2_r <= #1 imm2;
|
rd_addr_r <= #1 rd_addr[7];
|
rd_addr_r <= #1 rd_addr[7];
|
op1_r <= #1 op1_out;
|
op1_r <= #1 op1_out;
|
dack_ir <= #1 dack_i;
|
dack_ir <= #1 dack_i;
|
sp_r <= #1 sp;
|
sp_r <= #1 sp;
|
|
pc_wr_r <= #1 pc_wr && (pc_wr_sel !== `OC8051_PIS_AH);
|
|
pc_wr_r2 <= #1 pc_wr_r;
|
end
|
end
|
|
|
|
always @(posedge clk or posedge rst)
|
|
if (rst) begin
|
|
inc_pc_r <= #1 1'b1;
|
|
end else if (istb) begin
|
|
inc_pc_r <= #1 inc_pc;
|
|
end
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
