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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2003/01/13 14:14:41 simont
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// replace some modules
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//
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// Revision 1.6 2002/09/30 17:33:59 simont
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// Revision 1.6 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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//
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//
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//
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//
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// synopsys translate_on
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// synopsys translate_on
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_ports (clk, rst, bit_in, data_in, wr, wr_bit, wr_addr, rd_addr, rmw, data_out, bit_out, p0_out, p1_out, p2_out, p3_out,
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module oc8051_ports (clk, rst,
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p0_in, p1_in, p2_in, p3_in);
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bit_in, data_in,
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wr, wr_bit,
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wr_addr, rmw,
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p0_out, p1_out, p2_out, p3_out,
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p0_in, p1_in, p2_in, p3_in,
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p0_data, p1_data, p2_data, p3_data);
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//
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//
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// clk (in) clock
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// clk (in) clock
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// rst (in) reset
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// rst (in) reset
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// bit_in (in) bit input [oc8051_alu.desCy]
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// bit_in (in) bit input [oc8051_alu.desCy]
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// data_in (in) data input (from alu destiantion 1) [oc8051_alu.des1]
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// data_in (in) data input (from alu destiantion 1) [oc8051_alu.des1]
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// p0_in, p1_in, p2_in, p3_in (in) port inputs [pin]
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// p0_in, p1_in, p2_in, p3_in (in) port inputs [pin]
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//
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//
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input clk, rst, wr, wr_bit, bit_in, rmw;
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input clk, rst, wr, wr_bit, bit_in, rmw;
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input [7:0] wr_addr, rd_addr, data_in, p0_in, p1_in, p2_in, p3_in;
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input [7:0] wr_addr, data_in, p0_in, p1_in, p2_in, p3_in;
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output [7:0] p0_out, p1_out, p2_out, p3_out;
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output [7:0] p0_data, p1_data, p2_data, p3_data;
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output bit_out;
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reg [7:0] p0_out, p1_out, p2_out, p3_out;
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output [7:0] data_out, p0_out, p1_out, p2_out, p3_out;
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reg bit_out;
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assign p0_data = rmw ? p0_out : p0_in;
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reg [7:0] data_out, p0_out, p1_out, p2_out, p3_out;
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assign p1_data = rmw ? p1_out : p1_in;
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assign p2_data = rmw ? p2_out : p2_in;
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assign p3_data = rmw ? p3_out : p3_in;
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//
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//
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// case of writing to port
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// case of writing to port
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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endcase
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endcase
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end
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end
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end
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end
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end
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end
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//always @(p0_out or p0_in or p1_out or p1_in or p2_out or p2_in or p3_out or p3_in or rmw)
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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data_out <= #1 8'h0;
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else if (rmw) begin
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if ((rd_addr==wr_addr) & wr & !wr_bit)
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data_out <= #1 data_in;
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else begin
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case (rd_addr[5:4])
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2'b00: data_out <= #1 p0_out;
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2'b01: data_out <= #1 p1_out;
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2'b10: data_out <= #1 p2_out;
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2'b11: data_out <= #1 p3_out;
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endcase
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end
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end else
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case (rd_addr[5:4])
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2'b00: data_out <= #1 p0_in;
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2'b01: data_out <= #1 p1_in;
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2'b10: data_out <= #1 p2_in;
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2'b11: data_out <= #1 p3_in;
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endcase
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end
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//always @(rmw or rd_addr or p0_out or p1_out or p2_out or p3_out or p0_in or p1_in or p2_in or p3_in)
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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bit_out <= #1 1'b0;
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else if (rmw) begin
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if ((wr_addr==rd_addr) & wr & wr_bit)
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bit_out <= #1 bit_in;
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else if ((wr_addr[7:3]==rd_addr[7:3]) & wr)
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bit_out <= #1 data_in[rd_addr[2:0]];
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else begin
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case (rd_addr[7:3])
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`OC8051_SFR_B_P0: bit_out <= #1 p0_out[rd_addr[2:0]];
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`OC8051_SFR_B_P1: bit_out <= #1 p1_out[rd_addr[2:0]];
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`OC8051_SFR_B_P2: bit_out <= #1 p2_out[rd_addr[2:0]];
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default: bit_out <= #1 p3_out[rd_addr[2:0]];
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endcase
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end
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end else begin
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case (rd_addr[7:3])
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`OC8051_SFR_B_P0: bit_out <= #1 p0_in[rd_addr[2:0]];
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`OC8051_SFR_B_P1: bit_out <= #1 p1_in[rd_addr[2:0]];
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`OC8051_SFR_B_P2: bit_out <= #1 p2_in[rd_addr[2:0]];
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default: bit_out <= #1 p3_in[rd_addr[2:0]];
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endcase
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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