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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2003/04/07 14:58:02 simont
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// change sfr's interface.
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//
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// Revision 1.7 2003/01/13 14:14:41 simont
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// Revision 1.7 2003/01/13 14:14:41 simont
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// replace some modules
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// replace some modules
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//
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//
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// Revision 1.6 2002/09/30 17:33:59 simont
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// Revision 1.6 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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// synopsys translate_on
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// synopsys translate_on
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_ports (clk, rst,
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module oc8051_ports (clk,
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bit_in, data_in,
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rst,
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wr, wr_bit,
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bit_in,
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wr_addr, rmw,
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data_in,
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p0_out, p1_out, p2_out, p3_out,
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wr,
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p0_in, p1_in, p2_in, p3_in,
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wr_bit,
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p0_data, p1_data, p2_data, p3_data);
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wr_addr,
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//
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// clk (in) clock
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`ifdef OC8051_PORT0
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// rst (in) reset
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p0_out,
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// bit_in (in) bit input [oc8051_alu.desCy]
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p0_in,
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// data_in (in) data input (from alu destiantion 1) [oc8051_alu.des1]
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p0_data,
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// wr (in) write [oc8051_decoder.wr -r]
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`endif
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// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
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// wr_addr (in) write address [oc8051_ram_wr_sel.out]
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`ifdef OC8051_PORT1
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// rd_addr (in) read address [oc8051_ram_rd_sel.out]
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p1_out,
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// rmw (in) read modify write feature [oc8051_decoder.rmw]
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p1_in,
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// data_out (out) data output [oc8051_ram_sel.ports_in]
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p1_data,
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// p0_out, p1_out, p2_out, p3_out (out) port outputs [pin]
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// p0_in, p1_in, p2_in, p3_in (in) port inputs [pin]
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`endif
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//
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`ifdef OC8051_PORT2
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p2_out,
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p2_in,
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p2_data,
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`endif
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`ifdef OC8051_PORT3
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p3_out,
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p3_in,
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p3_data,
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`endif
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rmw);
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input clk, //clock
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rst, //reset
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wr, //write [oc8051_decoder.wr -r]
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wr_bit, //write bit addresable [oc8051_decoder.bit_addr -r]
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bit_in, //bit input [oc8051_alu.desCy]
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rmw; //read modify write feature [oc8051_decoder.rmw]
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input [7:0] wr_addr, //write address [oc8051_ram_wr_sel.out]
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data_in; //data input (from alu destiantion 1) [oc8051_alu.des1]
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`ifdef OC8051_PORT0
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input [7:0] p0_in;
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output [7:0] p0_out,
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p0_data;
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reg [7:0] p0_out;
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input clk, rst, wr, wr_bit, bit_in, rmw;
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assign p0_data = rmw ? p0_out : p0_in;
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input [7:0] wr_addr, data_in, p0_in, p1_in, p2_in, p3_in;
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`endif
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output [7:0] p0_out, p1_out, p2_out, p3_out;
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output [7:0] p0_data, p1_data, p2_data, p3_data;
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reg [7:0] p0_out, p1_out, p2_out, p3_out;
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`ifdef OC8051_PORT1
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input [7:0] p1_in;
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output [7:0] p1_out,
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p1_data;
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reg [7:0] p1_out;
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assign p0_data = rmw ? p0_out : p0_in;
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assign p1_data = rmw ? p1_out : p1_in;
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assign p1_data = rmw ? p1_out : p1_in;
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`endif
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`ifdef OC8051_PORT2
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input [7:0] p2_in;
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output [7:0] p2_out,
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p2_data;
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reg [7:0] p2_out;
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assign p2_data = rmw ? p2_out : p2_in;
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assign p2_data = rmw ? p2_out : p2_in;
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`endif
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`ifdef OC8051_PORT3
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input [7:0] p3_in;
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output [7:0] p3_out,
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p3_data;
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reg [7:0] p3_out;
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assign p3_data = rmw ? p3_out : p3_in;
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assign p3_data = rmw ? p3_out : p3_in;
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`endif
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//
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//
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// case of writing to port
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// case of writing to port
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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`ifdef OC8051_PORT0
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p0_out <= #1 `OC8051_RST_P0;
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p0_out <= #1 `OC8051_RST_P0;
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`endif
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`ifdef OC8051_PORT1
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p1_out <= #1 `OC8051_RST_P1;
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p1_out <= #1 `OC8051_RST_P1;
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`endif
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`ifdef OC8051_PORT2
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p2_out <= #1 `OC8051_RST_P2;
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p2_out <= #1 `OC8051_RST_P2;
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`endif
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`ifdef OC8051_PORT3
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p3_out <= #1 `OC8051_RST_P3;
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p3_out <= #1 `OC8051_RST_P3;
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`endif
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end else if (wr) begin
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end else if (wr) begin
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if (!wr_bit) begin
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if (!wr_bit) begin
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case (wr_addr)
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case (wr_addr)
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//
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//
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// bytaddresable
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// bytaddresable
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`ifdef OC8051_PORT0
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`OC8051_SFR_P0: p0_out <= #1 data_in;
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`OC8051_SFR_P0: p0_out <= #1 data_in;
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`endif
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`ifdef OC8051_PORT1
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`OC8051_SFR_P1: p1_out <= #1 data_in;
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`OC8051_SFR_P1: p1_out <= #1 data_in;
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`endif
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`ifdef OC8051_PORT2
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`OC8051_SFR_P2: p2_out <= #1 data_in;
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`OC8051_SFR_P2: p2_out <= #1 data_in;
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`endif
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`ifdef OC8051_PORT3
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`OC8051_SFR_P3: p3_out <= #1 data_in;
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`OC8051_SFR_P3: p3_out <= #1 data_in;
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`endif
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endcase
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endcase
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end else begin
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end else begin
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case (wr_addr[7:3])
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case (wr_addr[7:3])
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//
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//
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// bit addressable
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// bit addressable
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`ifdef OC8051_PORT0
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`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
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`endif
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`ifdef OC8051_PORT1
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`OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
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`endif
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`ifdef OC8051_PORT2
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`OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
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`endif
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`ifdef OC8051_PORT3
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`OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
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`endif
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endcase
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endcase
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end
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end
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end
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end
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end
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end
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