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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_ports.v] - Diff between revs 120 and 179
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| Rev 120 |
Rev 179 |
| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2003/04/10 12:43:19 simont
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// defines for pherypherals added
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//
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// Revision 1.8 2003/04/07 14:58:02 simont
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// Revision 1.8 2003/04/07 14:58:02 simont
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// change sfr's interface.
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// change sfr's interface.
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//
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//
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// Revision 1.7 2003/01/13 14:14:41 simont
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// Revision 1.7 2003/01/13 14:14:41 simont
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// replace some modules
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// replace some modules
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| Line 166... |
Line 169... |
`ifdef OC8051_PORT3
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`ifdef OC8051_PORT3
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p3_out <= #1 `OC8051_RST_P3;
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p3_out <= #1 `OC8051_RST_P3;
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`endif
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`endif
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end else if (wr) begin
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end else if (wr) begin
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if (!wr_bit) begin
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if (!wr_bit) begin
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case (wr_addr)
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case (wr_addr) /* synopsys full_case parallel_case */
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//
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//
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// bytaddresable
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// bytaddresable
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`ifdef OC8051_PORT0
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`ifdef OC8051_PORT0
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`OC8051_SFR_P0: p0_out <= #1 data_in;
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`OC8051_SFR_P0: p0_out <= #1 data_in;
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`endif
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`endif
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| Line 186... |
Line 189... |
`ifdef OC8051_PORT3
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`ifdef OC8051_PORT3
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`OC8051_SFR_P3: p3_out <= #1 data_in;
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`OC8051_SFR_P3: p3_out <= #1 data_in;
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`endif
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`endif
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endcase
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endcase
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end else begin
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end else begin
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case (wr_addr[7:3])
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case (wr_addr[7:3]) /* synopsys full_case parallel_case */
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//
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//
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// bit addressable
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// bit addressable
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`ifdef OC8051_PORT0
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`ifdef OC8051_PORT0
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`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
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