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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_ports.v] - Diff between revs 15 and 22
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| Rev 15 |
Rev 22 |
| Line 143... |
Line 143... |
if (rst)
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if (rst)
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bit_out <= #1 1'b0;
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bit_out <= #1 1'b0;
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else if (rmw) begin
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else if (rmw) begin
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if ((wr_addr==rd_addr) & wr & wr_bit)
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if ((wr_addr==rd_addr) & wr & wr_bit)
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bit_out <= #1 bit_in;
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bit_out <= #1 bit_in;
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else if ((wr_addr[7:3]==rd_addr[7:3]) & wr & !wr_bit)
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bit_out <= #1 data_in[rd_addr[2:0]];
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else begin
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else begin
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case (rd_addr[7:3])
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case (rd_addr[7:3])
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`OC8051_SFR_B_P0: bit_out <= #1 p0_out[rd_addr[2:0]];
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`OC8051_SFR_B_P0: bit_out <= #1 p0_out[rd_addr[2:0]];
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`OC8051_SFR_B_P1: bit_out <= #1 p1_out[rd_addr[2:0]];
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`OC8051_SFR_B_P1: bit_out <= #1 p1_out[rd_addr[2:0]];
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`OC8051_SFR_B_P2: bit_out <= #1 p2_out[rd_addr[2:0]];
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`OC8051_SFR_B_P2: bit_out <= #1 p2_out[rd_addr[2:0]];
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