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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2003/04/03 19:17:19 simont
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// add `include "oc8051_defines.v"
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//
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// Revision 1.1 2003/04/02 11:16:22 simont
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// Revision 1.1 2003/04/02 11:16:22 simont
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// initial inport
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// initial inport
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//
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//
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// Revision 1.4 2002/10/23 17:00:18 simont
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// Revision 1.4 2002/10/23 17:00:18 simont
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// signal es_int=1'b0
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// signal es_int=1'b0
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// prepared header
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// prepared header
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//
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//
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//
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//
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
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module oc8051_rom (rst, clk, addr, ea_int, data_o);
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//parameter INT_ROM_WID= 15;
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//parameter INT_ROM_WID= 15;
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input rst, clk;
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input rst, clk;
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input [15:0] addr;
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input [15:0] addr;
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//input [22:0] addr;
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//input [22:0] addr;
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output ea_int;
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output ea_int;
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output [7:0] data1, data2, data3;
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output [31:0] data_o;
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reg [7:0] data1, data2, data3;
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reg [31:0] data_o;
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wire ea;
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wire ea;
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reg ea_int;
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reg ea_int;
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Line 886... |
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`else
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`else
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reg [7:0] buff [0:65535]; //64kb
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reg [7:0] buff [0:65535]; //64kb
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//reg [7:0] buff [8388607:0]; //8Mb
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assign ea = 1'b0;
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assign ea = 1'b0;
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initial
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initial
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begin
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begin
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// for (i=0; i<65536; i=i+1)
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// buff [i] = 8'h00;
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$readmemh("../../../bench/in/oc8051_rom.in", buff);
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$readmemh("../../../bench/in/oc8051_rom.in", buff);
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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ea_int <= #1 1'b1;
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ea_int <= #1 1'b1;
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else ea_int <= #1 !ea;
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else ea_int <= #1 !ea;
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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data1 <= #1 buff [addr];
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data_o <= #1 {buff[addr+3], buff[addr+2], buff[addr+1], buff[addr]};
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data2 <= #1 buff [addr+1];
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data3 <= #1 buff [addr+2];
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end
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end
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`endif
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`endif
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