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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2003/04/09 15:49:42 simont
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// Register oc8051_sfr dato output, add signal wait_data.
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//
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// Revision 1.7 2003/04/07 14:58:02 simont
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// Revision 1.7 2003/04/07 14:58:02 simont
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// change sfr's interface.
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// change sfr's interface.
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//
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//
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// Revision 1.6 2003/04/07 13:29:16 simont
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// Revision 1.6 2003/04/07 13:29:16 simont
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// change uart to meet timing.
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// change uart to meet timing.
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Line 156... |
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input rst, clk, we, bit_in, desAc, desOv, rmw, rxd, t2, t2ex;
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input rst, clk, we, bit_in, desAc, desOv, rmw, rxd, t2, t2ex;
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input int_ack, int0, int1, reti, wr_bit, t0, t1;
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input int_ack, int0, int1, reti, wr_bit, t0, t1;
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input [1:0] psw_set;
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input [1:0] psw_set, wr_sfr;
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input [2:0] ram_rd_sel, ram_wr_sel, wr_sfr;
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input [2:0] ram_rd_sel, ram_wr_sel;
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input [7:0] adr0, adr1, dat1, dat2, p0_in, p1_in, p2_in, p3_in;
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input [7:0] adr0, adr1, dat1, dat2, p0_in, p1_in, p2_in, p3_in;
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output bit_out, txd, intr, srcAc, cy, wait_data;
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output bit_out, txd, intr, srcAc, cy, wait_data;
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output [1:0] bank_sel;
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output [1:0] bank_sel;
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output [7:0] dat0, p0_out, p1_out, p2_out, p3_out, int_src, dptr_hi, dptr_lo, acc;
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output [7:0] dat0, p0_out, p1_out, p2_out, p3_out, int_src, dptr_hi, dptr_lo, acc;
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//
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//
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// b register
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// b register
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// B
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// B
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oc8051_b_register oc8051_b_register (.clk(clk), .rst(rst), .bit_in(bit_in),
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oc8051_b_register oc8051_b_register (.clk(clk), .rst(rst), .bit_in(bit_in),
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.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1),
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.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1),
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.data_out(b_reg), .wr_sfr(wr_sfr));
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.data_out(b_reg));
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//
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//
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//stack pointer
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//stack pointer
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// SP
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// SP
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oc8051_sp oc8051_sp1(.clk(clk), .rst(rst), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel),
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oc8051_sp oc8051_sp1(.clk(clk), .rst(rst), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel),
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dat0 <= #1 dat1;
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dat0 <= #1 dat1;
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wait_data <= #1 1'b0;
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wait_data <= #1 1'b0;
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end else if (
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end else if (
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(((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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(((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) | //write to dpl
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((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) | //write to dpl
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((wr_sfr==`OC8051_WRS_BA) & (adr0==`OC8051_SFR_B)) | //write to b
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// ((wr_sfr==`OC8051_WRS_BA) & (adr0==`OC8051_SFR_B)) | //write to b
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(adr1[7] & (adr1==adr0) & we & !wr_bit_r)) & !wait_data) begin //write and read same address
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(adr1[7] & (adr1==adr0) & we & !wr_bit_r)) & !wait_data) begin //write and read same address
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// dat0 <= #1 dat1;
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// dat0 <= #1 dat1;
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wait_data <= #1 1'b1;
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wait_data <= #1 1'b1;
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end else if (
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end else if (
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(((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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(((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) | //write to dph
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((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) //write to dph
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((wr_sfr==`OC8051_WRS_BA) & (adr0==`OC8051_SFR_ACC))) & !wait_data) begin //write to b
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// ((wr_sfr==`OC8051_WRS_BA) & (adr0==`OC8051_SFR_ACC))
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) & !wait_data) begin //write to b
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// dat0 <= #1 dat2;
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// dat0 <= #1 dat2;
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wait_data <= #1 1'b1;
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wait_data <= #1 1'b1;
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// else if (({adr1[7:3], 3'b000}==adr0_r) & we & wr_bit_r)
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// else if (({adr1[7:3], 3'b000}==adr0_r) & we & wr_bit_r)
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// dat0 <= #1 dat1;
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// dat0 <= #1 dat1;
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begin
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begin
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if (rst)
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if (rst)
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bit_out <= #1 1'h0;
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bit_out <= #1 1'h0;
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else if (
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else if (
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((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) |
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((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) |
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((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC)) | //write to acc
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((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC)) //write to acc
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((wr_sfr==`OC8051_WRS_BA) & (adr0[7:3]==`OC8051_SFR_B_B))) //write to b
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// ((wr_sfr==`OC8051_WRS_BA) & (adr0[7:3]==`OC8051_SFR_B_B))
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) //write to b
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bit_out <= #1 dat1[adr0[2:0]];
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bit_out <= #1 dat1[adr0[2:0]];
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else if ((adr1==adr0) & we & wr_bit_r)
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else if ((adr1==adr0) & we & wr_bit_r)
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bit_out <= #1 bit_in;
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bit_out <= #1 bit_in;
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else
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else
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