| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/11/05 17:22:27 simont
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// initial import
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module oc8051_sfr (rst, clk, adr0, adr1, dat0, dat1, dat2, we, bit_in, bit_out, wr_bit, wad2, acc,
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module oc8051_sfr (rst, clk, adr0, adr1, dat0, dat1, dat2, we, bit_in, bit_out, wr_bit,
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rd_x, xdata, ram_wr_sel, ram_rd_sel, sp, bank_sel, desAc, desOv, psw_set, srcAc, cy, rmw,
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wr_sfr, acc, ram_wr_sel, ram_rd_sel, sp, sp_w, bank_sel, desAc, desOv, psw_set, srcAc, cy, rmw,
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p0_out, p1_out, p2_out, p3_out, p0_in, p1_in, p2_in, p3_in, rxd, txd, int_ack, intr, int0,
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p0_out, p1_out, p2_out, p3_out, p0_in, p1_in, p2_in, p3_in, rxd, txd, int_ack, intr, int0,
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int1, reti, int_src, t0, t1, dptr_hi, dptr_lo);
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int1, reti, int_src, t0, t1, dptr_hi, dptr_lo, t2, t2ex);
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//
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//
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// rst (in) reset - pin
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// rst (in) reset - pin
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// clk (in) clock - pin
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// clk (in) clock - pin
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// adr0, adr1 (in) address input
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// adr0, adr1 (in) address input
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// dat0 (out) data output
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// dat0 (out) data output
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| Line 66... |
Line 69... |
// bit_in
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// bit_in
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// bit_out
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// bit_out
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// wr_bit
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// wr_bit
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// ram_rd_sel
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// ram_rd_sel
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// ram_wr_sel
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// ram_wr_sel
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// wr_sfr
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//////////
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//////////
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//
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//
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// acc:
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// acc:
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// wad2
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// acc
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// acc
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// rd_x
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// xdata
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//////////
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//////////
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//
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//
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// sp:
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// sp:
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// sp
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// sp
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//////////
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//////////
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| Line 110... |
Line 111... |
//////////
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//////////
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//
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//
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// timers/counters:
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// timers/counters:
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// t0
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// t0
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// t1
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// t1
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// t2
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// t2ex
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//
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//
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//////////
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//////////
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//
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//
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// dptr:
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// dptr:
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// dptr_hi
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// dptr_hi
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// dptr_lo
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// dptr_lo
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//
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//////////
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//
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input rst, clk, we, bit_in, desAc, desOv, rmw, rxd, t2, t2ex;
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input int_ack, int0, int1, reti, wr_bit, t0, t1;
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input [1:0] psw_set;
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input [2:0] ram_rd_sel, ram_wr_sel, wr_sfr;
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input [7:0] adr0, adr1, dat1, dat2, p0_in, p1_in, p2_in, p3_in;
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input rst, clk, we, bit_in, wad2, desAc, desOv, rmw, rxd, int_ack, int0, int1, reti, wr_bit, rd_x;
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output bit_out, txd, intr, srcAc, cy;
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input [1:0] ram_rd_sel, psw_set;
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input [2:0] ram_wr_sel;
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input [7:0] adr0, adr1, dat1, dat2, p0_in, p1_in, p2_in, p3_in, xdata;
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output bit_out, txd, intr, t0, t1, srcAc, cy;
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output [1:0] bank_sel;
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output [1:0] bank_sel;
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output [7:0] dat0, p0_out, p1_out, p2_out, p3_out, int_src, dptr_hi, dptr_lo, acc, sp;
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output [7:0] dat0, p0_out, p1_out, p2_out, p3_out, int_src, dptr_hi, dptr_lo, acc;
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output [7:0] sp, sp_w;
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reg bit_out;
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reg bit_out;
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reg [7:0] dat0, sp_r, adr0_r;
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reg [7:0] dat0, adr0_r;
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reg wr_bit_r;
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reg [2:0] ram_wr_sel_r;
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reg [2:0] ram_wr_sel_r;
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wire acc_bit, b_bit, psw_bit, port_bit, uart_bit, int_bit;
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wire acc_bit, b_bit, psw_bit, port_bit, uart_bit, int_bit, tc2_bit, pca_bit;
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wire p, int_uart, tf0, tf1, tr0, tr1;
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wire p, int_uart, tf0, tf1, tr0, tr1;
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wire [7:0] b_reg, psw, ports, uart, int_out, tc_out;
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wire dps, rclk, tclk, brate2, tc2_int;
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wire [7:0] b_reg, psw, ports, uart, int_out, tc_out, tc2, sp_out;
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assign cy = psw[7];
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assign cy = psw[7];
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assign srcAc = psw [6];
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assign srcAc = psw [6];
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//
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//
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// accumulator
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// accumulator
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// ACC
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// ACC
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oc8051_acc oc8051_acc1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1),
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oc8051_acc oc8051_acc1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1),
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.data2_in(dat2), .wr(we), .wr_bit(wr_bit), .wad2(wad2),
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.data2_in(dat2), .wr(we), .wr_bit(wr_bit_r), .wr_sfr(wr_sfr),
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.wr_addr(adr1), .rd_addr(adr0[2:0]), .data_out(acc), .bit_out(acc_bit), .p(p),
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.wr_addr(adr1), .rd_addr(adr0[2:0]), .data_out(acc), .bit_out(acc_bit), .p(p));
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.rd_x(rd_x), .xdata(xdata));
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//
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//
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// b register
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// b register
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// B
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// B
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oc8051_b_register oc8051_b_register (.clk(clk), .rst(rst), .bit_in(bit_in), .bit_out(b_bit),
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oc8051_b_register oc8051_b_register (.clk(clk), .rst(rst), .bit_in(bit_in), .bit_out(b_bit),
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.data_in(dat1), .wr(we), .wr_bit(wr_bit), .wr_addr(adr1), .rd_addr(adr0[2:0]),
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.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1), .rd_addr(adr0[2:0]),
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.data_out(b_reg));
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.data_out(b_reg), .wr_sfr(wr_sfr));
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//
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//
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//stack pointer
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//stack pointer
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// SP
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// SP
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oc8051_sp oc8051_sp1(.clk(clk), .rst(rst), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel),
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oc8051_sp oc8051_sp1(.clk(clk), .rst(rst), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel),
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.wr_addr(adr1), .wr(we), .wr_bit(wr_bit), .data_in(dat1),
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.wr_addr(adr1), .wr(we), .wr_bit(wr_bit_r), .data_in(dat1),
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.data_out(sp));
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.data_out(sp_out), .sp_out(sp), .sp_w(sp_w));
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//
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//
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//data pointer
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//data pointer
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// DPTR, DPH, DPL
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// DPTR, DPH, DPL
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oc8051_dptr oc8051_dptr1(.clk(clk), .rst(rst), .addr(adr1), .data_in(dat1),
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oc8051_dptr oc8051_dptr1(.clk(clk), .rst(rst), .addr(adr1), .data_in(dat1),
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.data2_in(dat2), .wr(we), .wr_bit(wr_bit), .wd2(ram_wr_sel_r),
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.data2_in(dat2), .wr(we), .wr_bit(wr_bit_r),
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.data_hi(dptr_hi), .data_lo(dptr_lo));
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.data_hi(dptr_hi), .data_lo(dptr_lo), .wr_sfr(wr_sfr));
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//
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//
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//program status word
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//program status word
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// PSW
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// PSW
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oc8051_psw oc8051_psw1 (.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0[2:0]), .data_in(dat1),
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oc8051_psw oc8051_psw1 (.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0[2:0]), .data_in(dat1),
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.wr(we), .wr_bit(wr_bit), .data_out(psw), .bit_out(psw_bit), .p(p), .cy_in(bit_in),
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.wr(we), .wr_bit(wr_bit_r), .data_out(psw), .bit_out(psw_bit), .p(p), .cy_in(bit_in),
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.ac_in(desAc), .ov_in(desOv), .set(psw_set), .bank_sel(bank_sel));
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.ac_in(desAc), .ov_in(desOv), .set(psw_set), .bank_sel(bank_sel));
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//
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//
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// ports
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// ports
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// P0, P1, P2, P3
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// P0, P1, P2, P3
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oc8051_ports oc8051_ports1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1), .wr(we),
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oc8051_ports oc8051_ports1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1), .wr(we),
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.wr_bit(wr_bit), .wr_addr(adr1), .rd_addr(adr0), .rmw(rmw),
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.wr_bit(wr_bit_r), .wr_addr(adr1), .rd_addr(adr0), .rmw(rmw),
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.data_out(ports), .bit_out(port_bit), .p0_out(p0_out), .p1_out(p1_out),
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.data_out(ports), .bit_out(port_bit), .p0_out(p0_out), .p1_out(p1_out),
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.p2_out(p2_out), .p3_out(p3_out), .p0_in(p0_in), .p1_in(p1_in), .p2_in(p2_in),
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.p2_out(p2_out), .p3_out(p3_out), .p0_in(p0_in), .p1_in(p1_in), .p2_in(p2_in),
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.p3_in(p3_in));
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.p3_in(p3_in));
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//
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//
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// serial interface
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// serial interface
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// SCON, SBUF
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// SCON, SBUF
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oc8051_uart oc8051_uatr1 (.clk(clk), .rst(rst), .bit_in(bit_in), .rd_addr(adr0),
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oc8051_uart oc8051_uatr1 (.clk(clk), .rst(rst), .bit_in(bit_in), .rd_addr(adr0),
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.data_in(dat1), .wr(we), .wr_bit(wr_bit), .wr_addr(adr1),
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.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1),
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.data_out(uart), .bit_out(uart_bit), .rxd(rxd), .txd(txd), .intr(int_uart),
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.data_out(uart), .bit_out(uart_bit), .rxd(rxd), .txd(txd), .intr(uart_int),
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.t1_ow(tf1));
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.t1_ow(tf1));
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//
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//
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// interrupt control
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// interrupt control
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// IP, IE, TCON
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// IP, IE, TCON
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oc0851_int oc8051_int1 (.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0), .bit_in(bit_in),
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oc0851_int oc8051_int1 (.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0), .bit_in(bit_in),
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.ack(int_ack), .intr(intr), .data_in(dat1), .data_out(int_out), .bit_out(int_bit),
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.ack(int_ack), .data_in(dat1), .data_out(int_out), .bit_out(int_bit),
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.wr(we), .wr_bit(wr_bit), .tf0(tf0), .tf1(tf1), .ie0(int0), .ie1(int1),
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.wr(we), .wr_bit(wr_bit_r),
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.reti(reti), .int_vec(int_src), .tr0(tr0), .tr1(tr1), .uart(int_uart));
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.tf0(tf0), .tf1(tf1), .t2_int(tc2_int), .tr0(tr0), .tr1(tr1),
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.ie0(int0), .ie1(int1),
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.uart_int(uart_int),
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.reti(reti), .intr(intr), .int_vec(int_src));
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//
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//
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// timer/counter control
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// timer/counter control
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// TH0, TH1, TL0, TH1, TMOD
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// TH0, TH1, TL0, TH1, TMOD
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oc8051_tc oc8051_tc1(.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0),
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oc8051_tc oc8051_tc1(.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0),
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.data_in(dat1), .wr(we), .wr_bit(wr_bit), .ie0(int0), .ie1(int1), .tr0(tr0),
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.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .ie0(int0), .ie1(int1), .tr0(tr0),
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.tr1(tr1), .t0(t0), .t1(t1), .data_out(tc_out), .tf0(tf0), .tf1(tf1));
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.tr1(tr1), .t0(t0), .t1(t1), .data_out(tc_out), .tf0(tf0), .tf1(tf1));
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//
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// timer/counter 2
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// TH2, TH2, RCAPL2L, RCAPL2H, T2CON, T2MOD
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oc8051_tc2 oc8051_tc21(.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0_r), .data_in(dat1), .wr(we),
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.wr_bit(wr_bit_r), .bit_in(bit_in), .t2(t2), .t2ex(t2ex), .data_out(tc2), .bit_out(tc2_bit),
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.rclk(rclk), .tclk(tclk), .brate2(brate2), .tc2_int(tc2_int));
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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sp_r <= #1 8'h00;
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adr0_r <= #1 8'h00;
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adr0_r <= #1 8'h00;
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ram_wr_sel_r <= #1 3'b000;
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ram_wr_sel_r <= #1 3'b000;
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wr_bit_r <= #1 1'b0;
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end else begin
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end else begin
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sp_r <= #1 sp;
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adr0_r <= #1 adr0;
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adr0_r <= #1 adr0;
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ram_wr_sel_r <= #1 ram_wr_sel;
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ram_wr_sel_r <= #1 ram_wr_sel;
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wr_bit_r <= #1 wr_bit;
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end
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end
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//
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//
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//set output in case of address (byte)
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//set output in case of address (byte)
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always @(adr0_r or psw or acc or dptr_hi or ports or sp_r or b_reg or uart or tc_out or int_out or dptr_lo)
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always @(adr0_r or psw or acc or dptr_hi or ports or sp_out or b_reg or uart or
|
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tc_out or tc2 or int_out or dptr_lo)
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begin
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begin
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case (adr0_r)
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case (adr0_r)
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`OC8051_SFR_ACC: dat0 = acc;
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`OC8051_SFR_ACC: dat0 = acc;
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`OC8051_SFR_PSW: dat0 = psw;
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`OC8051_SFR_PSW: dat0 = psw;
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`OC8051_SFR_P0: dat0 = ports;
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`OC8051_SFR_P0: dat0 = ports;
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`OC8051_SFR_P1: dat0 = ports;
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`OC8051_SFR_P1: dat0 = ports;
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`OC8051_SFR_P2: dat0 = ports;
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`OC8051_SFR_P2: dat0 = ports;
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`OC8051_SFR_P3: dat0 = ports;
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`OC8051_SFR_P3: dat0 = ports;
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`OC8051_SFR_SP: dat0 = sp_r;
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`OC8051_SFR_SP: dat0 = sp_out;
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`OC8051_SFR_B: dat0 = b_reg;
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`OC8051_SFR_B: dat0 = b_reg;
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`OC8051_SFR_DPTR_HI: dat0 = dptr_hi;
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`OC8051_SFR_DPTR_HI: dat0 = dptr_hi;
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`OC8051_SFR_DPTR_LO: dat0 = dptr_lo;
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`OC8051_SFR_DPTR_LO: dat0 = dptr_lo;
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`OC8051_SFR_SCON: dat0 = uart;
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`OC8051_SFR_SCON: dat0 = uart;
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`OC8051_SFR_SBUF: dat0 = uart;
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`OC8051_SFR_SBUF: dat0 = uart;
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| Line 247... |
Line 274... |
`OC8051_SFR_TL1: dat0 = tc_out;
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`OC8051_SFR_TL1: dat0 = tc_out;
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`OC8051_SFR_TMOD: dat0 = tc_out;
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`OC8051_SFR_TMOD: dat0 = tc_out;
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`OC8051_SFR_IP: dat0 = int_out;
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`OC8051_SFR_IP: dat0 = int_out;
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`OC8051_SFR_IE: dat0 = int_out;
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`OC8051_SFR_IE: dat0 = int_out;
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`OC8051_SFR_TCON: dat0 = int_out;
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`OC8051_SFR_TCON: dat0 = int_out;
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`OC8051_SFR_RCAP2H: dat0 = tc2;
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`OC8051_SFR_RCAP2L: dat0 = tc2;
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`OC8051_SFR_TH2: dat0 = tc2;
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`OC8051_SFR_TL2: dat0 = tc2;
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`OC8051_SFR_T2MOD: dat0 = tc2;
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`OC8051_SFR_T2CON: dat0 = tc2;
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default: dat0 = 8'h00;
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default: dat0 = 8'h00;
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endcase
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endcase
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end
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end
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//
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//
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//set output in case of address (bit)
|
//set output in case of address (bit)
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always @(adr0_r or b_bit or acc_bit or psw_bit or int_bit or port_bit or uart_bit)
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always @(adr0_r or b_bit or acc_bit or psw_bit or int_bit or port_bit or uart_bit or tc2_bit)
|
begin
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begin
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case (adr0_r[7:3])
|
case (adr0_r[7:3])
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`OC8051_SFR_B_ACC: bit_out = acc_bit;
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`OC8051_SFR_B_ACC: bit_out = acc_bit;
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`OC8051_SFR_B_PSW: bit_out = psw_bit;
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`OC8051_SFR_B_PSW: bit_out = psw_bit;
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`OC8051_SFR_B_P0: bit_out = port_bit;
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`OC8051_SFR_B_P0: bit_out = port_bit;
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| Line 268... |
Line 302... |
`OC8051_SFR_B_B: bit_out = b_bit;
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`OC8051_SFR_B_B: bit_out = b_bit;
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`OC8051_SFR_B_IP: bit_out = int_bit;
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`OC8051_SFR_B_IP: bit_out = int_bit;
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`OC8051_SFR_B_IE: bit_out = int_bit;
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`OC8051_SFR_B_IE: bit_out = int_bit;
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`OC8051_SFR_B_TCON: bit_out = int_bit;
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`OC8051_SFR_B_TCON: bit_out = int_bit;
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`OC8051_SFR_B_SCON: bit_out = uart_bit;
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`OC8051_SFR_B_SCON: bit_out = uart_bit;
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`OC8051_SFR_B_T2CON: bit_out = tc2_bit;
|
default: bit_out = 1'b0;
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default: bit_out = 1'b0;
|
endcase
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endcase
|
end
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end
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endmodule
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endmodule
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