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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/11/05 17:23:54 simont
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// add module oc8051_sfr, 256 bytes internal ram
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//
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// Revision 1.3 2002/09/30 17:33:59 simont
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// Revision 1.3 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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//
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//
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//
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//
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_sp (clk, rst, ram_rd_sel, ram_wr_sel, wr_addr, wr, wr_bit, data_in, data_out);
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module oc8051_sp (clk, rst, ram_rd_sel, ram_wr_sel, wr_addr, wr, wr_bit, data_in, data_out, sp_out, sp_w);
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//
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// clk (in) clock
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// rst (in) reset
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// ram_rd_sel (in) ram read select, used tu calculate next value [oc8051_decoder.ram_rd_sel]
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// ram_wr_sel (in) ram write select, used tu calculate next value [oc8051_decoder.ram_wr_sel -r]
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// wr (in) write [oc8051_decoder.wr -r]
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// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
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// data_in (in) data input [oc8051_alu.des1]
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// wr_addr (in) write address (if is addres of sp and white high must be written to sp) [oc8051_ram_wr_sel.out]
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// data_out (out) data output
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//
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input clk, rst, wr, wr_bit;
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input clk, rst, wr, wr_bit;
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input [1:0] ram_rd_sel;
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input [2:0] ram_rd_sel, ram_wr_sel;
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input [2:0] ram_wr_sel;
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input [7:0] data_in, wr_addr;
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input [7:0] data_in, wr_addr;
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output [7:0] data_out;
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output [7:0] data_out;
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output [7:0] sp_out, sp_w;
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reg [7:0] data_out;
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reg [7:0] sp_out, sp_w;
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reg [7:0] temp;
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reg pop;
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reg pop, write;
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wire write;
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wire [7:0] temp1;
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wire [7:0] sp_t;
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assign temp1 = write ? data_in : temp;
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reg [7:0] sp;
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always @(wr_addr or wr or wr_bit)
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begin
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assign write = ((wr_addr==`OC8051_SFR_SP) & (wr) & !(wr_bit));
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if ((wr_addr==`OC8051_SFR_SP) & (wr) & !(wr_bit))
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write = 1'b1;
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assign sp_t= write ? data_in : sp;
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else
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write = 1'b0;
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assign data_out = sp;
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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temp <= #1 `OC8051_RST_SP;
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sp <= #1 `OC8051_RST_SP;
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else if (write)
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sp <= #1 data_in;
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else
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else
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temp <= #1 data_out;
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sp <= #1 sp_out;
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end
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end
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always @(temp1 or ram_wr_sel or pop or write)
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always @(sp or ram_wr_sel)
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begin
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//
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// push
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if (ram_wr_sel==`OC8051_RWS_SP) sp_w = sp + 8'h01;
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else sp_w = sp;
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end
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always @(sp_t or ram_wr_sel or pop or write)
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begin
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begin
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//
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//
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// push
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// push
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if (ram_wr_sel==`OC8051_RWS_SP) data_out = temp1+8'h01;
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if (write) sp_out = sp_t;
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else if (write) data_out = temp1;
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else if (ram_wr_sel==`OC8051_RWS_SP) sp_out = sp_t + 8'h01;
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else data_out = temp1 - {7'b0, pop};
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else sp_out = sp_t - {7'b0, pop};
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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