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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_tc.v] - Diff between revs 82 and 112

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Rev 82	Rev 112
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.5 2003/01/13 14:14:41 simont`
	`// replace some modules`
	`//`
`// Revision 1.4 2002/09/30 17:33:59 simont`	`// Revision 1.4 2002/09/30 17:33:59 simont`
`// prepared header`	`// prepared header`
`//`	`//`
`//`	`//`

Line 55...	Line 58...
`include "oc8051_timescale.v"	`include "oc8051_timescale.v"
`//synopsys translate_on`	`//synopsys translate_on`



`module oc8051_tc (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1, data_out,`	`module oc8051_tc (clk, rst,`
`tf0, tf1);`	`wr_addr, rd_addr,`
	`data_in, data_out,`
`input [7:0] wr_addr, data_in, rd_addr;`	`wr, wr_bit,`
`input clk, rst, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1;`	`ie0, ie1,`
	`tr0, tr1,`
	`t0, t1,`
	`tf0, tf1,`
	`pres_ow);`

	`input [7:0] wr_addr,`
	`data_in,`
	`rd_addr;`
	`input clk,`
	`rst,`
	`wr,`
	`wr_bit,`
	`ie0,`
	`ie1,`
	`tr0,`
	`tr1,`
	`t0,`
	`t1;`
`output [7:0] data_out;`	`output [7:0] data_out;`
`output tf0, tf1;`	`output tf0,`
	`tf1,`
	`pres_ow;`


`reg [7:0] tmod, tl0, th0, tl1, th1, data_out;`	`reg [7:0] tmod, tl0, th0, tl1, th1, data_out;`
`reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;`	`reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;`

	`reg pres_ow;`
	`reg [3:0] prescaler;`

`wire tc0_add, tc1_add;`	`wire tc0_add, tc1_add;`

`assign tc0_add = (tr0 & (!tmod[3] \| !ie0) & (!(tmod[2]) \| (tmod[2] & !t0 & t0_buff)));`	`assign tc0_add = (tr0 & (!tmod[3] \| !ie0) & ((!tmod[2] & pres_ow) \| (tmod[2] & !t0 & t0_buff)));`
`assign tc1_add = (tr1 & (!tmod[7] \| !ie1) & (!(tmod[6]) \| (tmod[6] & !t1 & t1_buff)));`	`assign tc1_add = (tr1 & (!tmod[7] \| !ie1) & ((!tmod[6] & pres_ow) \| (tmod[6] & !t1 & t1_buff)));`
`assign tf1= tf1_0 \| tf1_1;`	`assign tf1= tf1_0 \| tf1_1;`

`//`	`//`
`// read or write from one of the addresses in tmod`	`// read or write from one of the addresses in tmod`
`//`	`//`
Line 132...	Line 159...
`OC8051_MODE3: begin // mode 3	`OC8051_MODE3: begin // mode 3

`if (tc0_add)`	`if (tc0_add)`
`{tf0, tl0} <= #1 {1'b0, tl0} +1'b1;`	`{tf0, tl0} <= #1 {1'b0, tl0} +1'b1;`

`if (tr1)`	`if (tr1 & pres_ow)`
`{tf1_0, th0} <= #1 {1'b0, th0} +1'b1;`	`{tf1_0, th0} <= #1 {1'b0, th0} +1'b1;`

`end`	`end`
`default:begin`	`default:begin`
`tf0 <= #1 1'b0;`	`tf0 <= #1 1'b0;`
Line 207...	Line 234...
`default: data_out <= #1 tmod;`	`default: data_out <= #1 tmod;`
`endcase`	`endcase`
`end`	`end`
`end`	`end`

	`always @(posedge clk or posedge rst)`
	`begin`
	`if (rst) begin`
	`prescaler <= #1 4'h0;`
	`pres_ow <= #1 1'b0;`
	`end else if (prescaler==4'b1011) begin`
	`prescaler <= #1 4'h0;`
	`pres_ow <= #1 1'b1;`
	`end else begin`
	`prescaler <= #1 prescaler + 4'h1;`
	`pres_ow <= #1 1'b0;`
	`end`
	`end`

`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`
`if (rst) begin`	`if (rst) begin`
`t0_buff <= #1 1'b0;`	`t0_buff <= #1 1'b0;`
`t1_buff <= #1 1'b0;`	`t1_buff <= #1 1'b0;`

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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_tc.v] - Diff between revs 82 and 112