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Line 41... |
input [7:0] wr_addr, data_in, rd_addr;
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input [7:0] wr_addr, data_in, rd_addr;
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input clk, rst, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1;
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input clk, rst, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1;
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output [7:0] data_out;
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output [7:0] data_out;
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output tf0, tf1;
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output tf0, tf1;
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reg [7:0] tmod, tl0, th0, tl1, th1, data_out;
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reg [7:0] tmod, tl0, th0, tl1, th1, data_out;
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reg [1:0] tmp0, tmp1;
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reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;
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reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;
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wire tc0_add, tc1_add;
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wire tc0_add, tc1_add;
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assign tc0_add = (tr0 & (!tmod[3] | !ie0) & (!(tmod[2]) | (tmod[2] & !t0 & t0_buff)));
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assign tc0_add = (tr0 & (!tmod[3] | !ie0) & (!(tmod[2]) | (tmod[2] & !t0 & t0_buff)));
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assign tc1_add = (tr1 & (!tmod[7] | !ie0) & (!(tmod[6]) | (tmod[6] & !t1 & t1_buff)));
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assign tc1_add = (tr1 & (!tmod[7] | !ie1) & (!(tmod[6]) | (tmod[6] & !t1 & t1_buff)));
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assign tf1= tf1_0 | tf1_1;
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assign tf1= tf1_0 | tf1_1;
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//
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//
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// read or write from one of the addresses in tmod
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// read or write from one of the addresses in tmod
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//
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//
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