URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_tc.v] - Diff between revs 46 and 82

Rev 46	Rev 82
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`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.4 2002/09/30 17:33:59 simont`
	`// prepared header`
	`//`
`//`	`//`

`include "oc8051_defines.v"	`include "oc8051_defines.v"

`//synopsys translate_off`	`//synopsys translate_off`
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`module oc8051_tc (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1, data_out,`	`module oc8051_tc (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1, data_out,`
`tf0, tf1);`	`tf0, tf1);`

`input [7:0] wr_addr, data_in, rd_addr;`	`input [7:0] wr_addr, data_in, rd_addr;`
`input clk, rst, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1;`	`input clk, rst, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1;`
`output [7:0] data_out;`	`output [7:0] data_out;`
`output tf0, tf1;`	`output tf0, tf1;`

`reg [7:0] tmod, tl0, th0, tl1, th1, data_out;`	`reg [7:0] tmod, tl0, th0, tl1, th1, data_out;`
`reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;`	`reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;`

`wire tc0_add, tc1_add;`	`wire tc0_add, tc1_add;`