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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_top.v] - Diff between revs 122 and 132

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Rev 122	Rev 132
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.24 2003/04/11 10:05:59 simont`
	`// deifne OC8051_ROM added`
	`//`
`// Revision 1.23 2003/04/10 12:43:19 simont`	`// Revision 1.23 2003/04/10 12:43:19 simont`
`// defines for pherypherals added`	`// defines for pherypherals added`
`//`	`//`
`// Revision 1.22 2003/04/09 16:24:04 simont`	`// Revision 1.22 2003/04/09 16:24:04 simont`
`// change wr_sft to 2 bit wire.`	`// change wr_sft to 2 bit wire.`
Line 275...	Line 278...

`wire [7:0] src1, //alu sources 1`	`wire [7:0] src1, //alu sources 1`
`src2, //alu sources 2`	`src2, //alu sources 2`
`src3, //alu sources 3`	`src3, //alu sources 3`
`des1, //alu destination 1`	`des1, //alu destination 1`
`des2, //alu destinations 2`	`des2; //alu destinations 2`
`des1_r; //destination 1 registerd (to comp1)`
`wire desCy, //carry out`	`wire desCy, //carry out`
`desAc,`	`desAc,`
`desOv, //overflow`	`desOv, //overflow`
`alu_cy,`	`alu_cy,`
`wr, //write to data ram`	`wr, //write to data ram`
Line 297...	Line 299...
`wire [1:0] comp_sel; //select source1 and source2 to compare`	`wire [1:0] comp_sel; //select source1 and source2 to compare`
`wire eq, //result (from comp1 to decoder)`	`wire eq, //result (from comp1 to decoder)`
`srcAc,`	`srcAc,`
`cy,`	`cy,`
`rd_ind,`	`rd_ind,`
`wr_ind;`	`wr_ind,`
	`comp_wait;`
`wire [2:0] op1_cur;`	`wire [2:0] op1_cur;`

`wire bit_addr, //bit addresable instruction`	`wire bit_addr, //bit addresable instruction`
`bit_data, //bit data from ram to ram_select`	`bit_data, //bit data from ram to ram_select`
`bit_out, //bit data from ram_select to alu and cy_select`	`bit_out, //bit data from ram_select to alu and cy_select`
Line 351...	Line 354...
`//`	`//`
`//alu`	`//alu`
`oc8051_alu oc8051_alu1(.rst(wb_rst_i),`	`oc8051_alu oc8051_alu1(.rst(wb_rst_i),`
`.clk(wb_clk_i),`	`.clk(wb_clk_i),`
`.op_code(alu_op),`	`.op_code(alu_op),`
`.rd(rd),`
`.src1(src1),`	`.src1(src1),`
`.src2(src2),`	`.src2(src2),`
`.src3(src3),`	`.src3(src3),`
`.srcCy(alu_cy),`	`.srcCy(alu_cy),`
`.srcAc(srcAc),`	`.srcAc(srcAc),`
`.des1(des1),`	`.des1(des1),`
`.des2(des2),`	`.des2(des2),`
`.des1_r(des1_r),`
`.desCy(desCy),`	`.desCy(desCy),`
`.desAc(desAc),`	`.desAc(desAc),`
`.desOv(desOv),`	`.desOv(desOv),`
`.bit_in(bit_out));`	`.bit_in(bit_out));`

Line 408...	Line 409...
`oc8051_comp oc8051_comp1(.sel(comp_sel),`	`oc8051_comp oc8051_comp1(.sel(comp_sel),`
`.eq(eq),`	`.eq(eq),`
`.b_in(bit_out),`	`.b_in(bit_out),`
`.cy(cy),`	`.cy(cy),`
`.acc(acc),`	`.acc(acc),`
`.des(des1_r));`	`.des(des1)`
	`// .comp_wait(comp_wait)`
	`);`


`//`	`//`
`//program rom`	`//program rom`
`ifdef OC8051_ROM	`ifdef OC8051_ROM
Line 519...	Line 522...
`.istb(istb),`	`.istb(istb),`
`.reti(reti),`	`.reti(reti),`

`//pc`	`//pc`
`.pc_wr_sel(pc_wr_sel),`	`.pc_wr_sel(pc_wr_sel),`
`.pc_wr(pc_wr),`	`.pc_wr(pc_wr & comp_wait),`
`.pc(pc),`	`.pc(pc),`

`// sfr's`	`// sfr's`
`.sp_w(sp_w),`	`.sp_w(sp_w),`
`.dptr({dptr_hi, dptr_lo}),`	`.dptr({dptr_hi, dptr_lo}),`
Line 549...	Line 552...
`.bit_out(sfr_bit),`	`.bit_out(sfr_bit),`
`.wr_bit(bit_addr_o),`	`.wr_bit(bit_addr_o),`
`.ram_rd_sel(ram_rd_sel),`	`.ram_rd_sel(ram_rd_sel),`
`.ram_wr_sel(ram_wr_sel),`	`.ram_wr_sel(ram_wr_sel),`
`.wr_sfr(wr_sfr),`	`.wr_sfr(wr_sfr),`
	`.comp_sel(comp_sel),`
	`.comp_wait(comp_wait),`
`// acc`	`// acc`
`.acc(acc),`	`.acc(acc),`
`// sp`	`// sp`
`.sp(sp),`	`.sp(sp),`
`.sp_w(sp_w),`	`.sp_w(sp_w),`

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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_top.v] - Diff between revs 122 and 132