| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.13 2002/09/30 17:33:59 simont
|
|
// prepared header
|
|
//
|
//
|
//
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
`include "oc8051_timescale.v"
|
`include "oc8051_timescale.v"
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
|
|
module oc8051_top (rst, clk, int0, int1, ea, rom_addr, op1, op2, op3, dat_i,
|
module oc8051_top (rst, clk, int0, int1, ea, iadr_o, idat_i,istb_o, iack_i, dat_i,
|
dat_o, adr_o, we_o, ack_i, stb_o, cyc_o, p0_in, p1_in, p2_in, p3_in, p0_out,
|
icyc_o, dat_o, adr_o, we_o, ack_i, stb_o, cyc_o, p0_in, p1_in, p2_in, p3_in, p0_out,
|
p1_out, p2_out, p3_out, rxd, txd, t0, t1);
|
p1_out, p2_out, p3_out, rxd, txd, t0, t1);
|
//
|
//
|
// rst (in) reset - pin
|
// rst (in) reset - pin
|
// clk (in) clock - pin
|
// clk (in) clock - pin
|
// rom_addr (out) program rom addres (pin + internal)
|
// iadr_o (out) program rom addres (pin + internal)
|
// int0 (in) external interrupt 0
|
// int0 (in) external interrupt 0
|
// int1 (in) external interrupt 1
|
// int1 (in) external interrupt 1
|
// dat_i (in) exteranal ram input
|
// dat_i (in) exteranal ram input
|
// dat_o (out) exteranal ram output
|
// dat_o (out) exteranal ram output
|
// adr_o (out) external address
|
// adr_o (out) external address
|
// we_o (out) write to external ram
|
// we_o (out) write to external ram
|
// stb_o
|
// stb_o
|
// ack_i
|
// ack_i
|
|
// idat_i (in) data from external program rom
|
|
// istb_o (out) strobe to program rom
|
|
// iack_i (in) acknowlage from external rom
|
|
// icyc_o (out)
|
// p0_in, p1_in, p2_in, p3_in (in) port inputs
|
// p0_in, p1_in, p2_in, p3_in (in) port inputs
|
// p0_out, p1_out, p2_out, p3_out (out) port outputs
|
// p0_out, p1_out, p2_out, p3_out (out) port outputs
|
// rxd (in) receive
|
// rxd (in) receive
|
// txd (out) transmit
|
// txd (out) transmit
|
// t0, t1 (in) t/c external inputs
|
// t0, t1 (in) t/c external inputs
|
//
|
//
|
//
|
//
|
|
|
|
|
|
|
input rst, clk, int0, int1, ea, rxd, t0, t1, ack_i;
|
input rst, clk, int0, int1, ea, rxd, t0, t1, ack_i, iack_i;
|
input [7:0] dat_i, p0_in, p1_in, p2_in, p3_in, op1, op2, op3;
|
input [7:0] dat_i, p0_in, p1_in, p2_in, p3_in;
|
|
input [31:0] idat_i;
|
|
|
output we_o, txd, stb_o, cyc_o;
|
output we_o, txd, stb_o, cyc_o, istb_o, icyc_o;
|
output [7:0] dat_o, p0_out, p1_out, p2_out, p3_out;
|
output [7:0] dat_o, p0_out, p1_out, p2_out, p3_out;
|
//output [15:0] rom_addr, ext_addr;
|
//output [15:0] rom_addr, ext_addr;
|
output [15:0] adr_o, rom_addr;
|
output [15:0] adr_o, iadr_o;
|
|
|
wire [7:0] op1_i, op2_i, op3_i, dptr_hi, dptr_lo, ri, data_out;
|
wire [7:0] op1_i, op2_i, op3_i, dptr_hi, dptr_lo, ri, data_out;
|
|
wire [7:0] op1, op2, op3;
|
wire [7:0] acc, b_reg, p0_out, p1_out, p2_out, p3_out, uart, tc_out, int_out;
|
wire [7:0] acc, b_reg, p0_out, p1_out, p2_out, p3_out, uart, tc_out, int_out;
|
|
|
wire [15:0] pc;
|
wire [15:0] pc;
|
|
|
//
|
//
|
// data output is always from accumulator
|
// data output is always from accumulator
|
assign dat_o = acc;
|
assign dat_o = acc;
|
|
|
assign cyc_o = stb_o;
|
assign cyc_o = stb_o;
|
|
assign icyc_o = istb_o;
|
|
|
|
|
|
assign op1 = idat_i[31:24];
|
|
assign op2 = idat_i[23:16];
|
|
assign op3 = idat_i[15:8];
|
|
|
//
|
//
|
// ram_rd_sel ram read (internal)
|
// ram_rd_sel ram read (internal)
|
// ram_wr_sel ram write (internal)
|
// ram_wr_sel ram write (internal)
|
// src_sel1, src_sel2 from decoder to register
|
// src_sel1, src_sel2 from decoder to register
|
| Line 125... |
Line 140... |
// int_uart interrupt from uart
|
// int_uart interrupt from uart
|
// tf0 interrupt from t/c 0
|
// tf0 interrupt from t/c 0
|
// tf1 interrupt from t/c 1
|
// tf1 interrupt from t/c 1
|
// tr0 timer 0 run
|
// tr0 timer 0 run
|
// tr1 timer 1 run
|
// tr1 timer 1 run
|
wire int_uart, tf0, tf1, tr0, tr1, reti, intr, ack;
|
wire int_uart, tf0, tf1, tr0, tr1, reti, intr, ack, istb;
|
wire [7:0] int_src;
|
wire [7:0] int_src;
|
|
|
//
|
//
|
//alu_op alu operation (from decoder)
|
//alu_op alu operation (from decoder)
|
//alu_op_r alu operation (registerd)
|
//alu_op_r alu operation (registerd)
|
| Line 218... |
Line 233... |
|
|
//
|
//
|
//program counter
|
//program counter
|
oc8051_pc oc8051_pc1(.rst(rst), .clk(clk), .pc_out(pc), .alu({des2,des1}),
|
oc8051_pc oc8051_pc1(.rst(rst), .clk(clk), .pc_out(pc), .alu({des2,des1}),
|
.pc_wr_sel(pc_wr_sel), .op1(op1_n), .op2(op2_n), .op3(op3_n), .wr(pc_wr),
|
.pc_wr_sel(pc_wr_sel), .op1(op1_n), .op2(op2_n), .op3(op3_n), .wr(pc_wr),
|
.rd(rd), .intr(intr));
|
.rd((rd && !(istb_o && !iack_i))), .intr(intr));
|
|
|
//
|
//
|
// decoder
|
// decoder
|
oc8051_decoder oc8051_decoder1(.clk(clk), .rst(rst), .op_in(op1_n), .ram_rd_sel(ram_rd_sel),
|
oc8051_decoder oc8051_decoder1(.clk(clk), .rst(rst), .op_in(op1_n), .ram_rd_sel(ram_rd_sel),
|
.ram_wr_sel(ram_wr_sel), .bit_addr(bit_addr), .src_sel1(src_sel1), .wr_xaddr(wr_xaddr),
|
.ram_wr_sel(ram_wr_sel), .bit_addr(bit_addr), .src_sel1(src_sel1), .wr_xaddr(wr_xaddr),
|
.src_sel2(src_sel2), .src_sel3(src_sel3), .alu_op(alu_op), .psw_set(psw_set),
|
.src_sel2(src_sel2), .src_sel3(src_sel3), .alu_op(alu_op), .psw_set(psw_set),
|
.imm_sel(imm_sel), .cy_sel(cy_sel), .wr(wr), .pc_wr(pc_wr), .pc_sel(pc_wr_sel),
|
.imm_sel(imm_sel), .cy_sel(cy_sel), .wr(wr), .pc_wr(pc_wr), .pc_sel(pc_wr_sel),
|
.comp_sel(comp_sel), .eq(eq), .rom_addr_sel(rom_addr_sel), .ext_addr_sel(ext_addr_sel),
|
.comp_sel(comp_sel), .eq(eq), .rom_addr_sel(rom_addr_sel), .ext_addr_sel(ext_addr_sel),
|
.wad2(wad2), .rd(rd), .we_o(we_o), .reti(reti), .rmw(rmw), .stb_o(stb_o), .ack_i(ack_i));
|
.wad2(wad2), .rd(rd), .we_o(we_o), .reti(reti), .rmw(rmw), .stb_o(stb_o), .ack_i(ack_i),
|
|
.istb(istb), .ea(ea && ea_int), .iack(iack_i));
|
|
|
|
|
|
|
//
|
//
|
// ram read and ram write select
|
// ram read and ram write select
|
| Line 292... |
Line 308... |
.wr_addr(wr_addr), .wr(wr_r), .wr_bit(bit_addr_r), .data_in(des1),
|
.wr_addr(wr_addr), .wr(wr_r), .wr_bit(bit_addr_r), .data_in(des1),
|
.data_out(sp), .data_out_r (sp_r));
|
.data_out(sp), .data_out_r (sp_r));
|
|
|
//
|
//
|
//program rom
|
//program rom
|
oc8051_rom oc8051_rom1(.rst(rst), .clk(clk), .ea_int(ea_int), .addr(rom_addr),
|
oc8051_rom oc8051_rom1(.rst(rst), .clk(clk), .ea_int(ea_int), .addr(iadr_o),
|
.data1(op1_i), .data2(op2_i), .data3(op3_i));
|
.data1(op1_i), .data2(op2_i), .data3(op3_i));
|
|
|
//
|
//
|
//data pointer
|
//data pointer
|
oc8051_dptr oc8051_dptr1(.clk(clk), .rst(rst), .addr(wr_addr), .data_in(des1),
|
oc8051_dptr oc8051_dptr1(.clk(clk), .rst(rst), .addr(wr_addr), .data_in(des1),
|
| Line 314... |
Line 330... |
.wr_bit(bit_addr_r), .data_out(psw), .data_out_r(psw_r), .bit_out(psw_bit), .p(p), .cy_in(desCy),
|
.wr_bit(bit_addr_r), .data_out(psw), .data_out_r(psw_r), .bit_out(psw_bit), .p(p), .cy_in(desCy),
|
.ac_in(desAc), .ov_in(desOv), .set(psw_set_r));
|
.ac_in(desAc), .ov_in(desOv), .set(psw_set_r));
|
|
|
//
|
//
|
//
|
//
|
oc8051_indi_addr oc8051_indi_addr1 (.clk(clk), .rst(rst), .addr(wr_addr), .data_in(des1),
|
oc8051_indi_addr oc8051_indi_addr1 (.clk(clk), .rst(rst), .addr(wr_addr),
|
.wr(wr_r), .wr_bit(bit_addr_r), .data_out(ri), .sel(op1_n[0]),
|
.data_in(des1), .wr(wr_r), .wr_bit(bit_addr_r), .data_out(ri),
|
.bank(psw[4:3]));
|
.sel(op1_n[0]), .bank(psw[4:3]));
|
|
|
//
|
//
|
//
|
//
|
oc8051_rom_addr_sel oc8051_rom_addr_sel1(.sel(rom_addr_sel),
|
oc8051_rom_addr_sel oc8051_rom_addr_sel1(.clk(clk), .rst(rst), .iack_i(iack_i),
|
.des1(des1), .des2(des2), .pc(pc), .out_addr(rom_addr));
|
.ea(ea && ea_int), .sel(rom_addr_sel), .des1(des1), .des2(des2),
|
|
.pc(pc), .out_addr(iadr_o));
|
|
|
//
|
//
|
//
|
//
|
oc8051_ext_addr_sel oc8051_ext_addr_sel1(.clk(clk), .rst(rst), .sel(ext_addr_sel),
|
oc8051_ext_addr_sel oc8051_ext_addr_sel1(.clk(clk), .rst(rst), .sel(ext_addr_sel),
|
.dptr_hi(dptr_hi), .dptr_lo(dptr_lo), .ri(ri), .addr_out(adr_o), .wr(wr_xaddr));
|
.dptr_hi(dptr_hi), .dptr_lo(dptr_lo), .ri(ri), .addr_out(adr_o), .wr(wr_xaddr));
|
| Line 348... |
Line 365... |
//
|
//
|
//
|
//
|
oc8051_op_select oc8051_op_select1(.clk(clk), .rst(rst), .ea(ea), .ea_int(ea_int), .op1_i(op1_i),
|
oc8051_op_select oc8051_op_select1(.clk(clk), .rst(rst), .ea(ea), .ea_int(ea_int), .op1_i(op1_i),
|
.op2_i(op2_i), .op3_i(op3_i), .op1_x(op1), .op2_x(op2), .op3_x(op3),
|
.op2_i(op2_i), .op3_i(op3_i), .op1_x(op1), .op2_x(op2), .op3_x(op3),
|
.op1_out(op1_n), .op2_out(op2_n), .op2_direct(op2_dr), .op3_out(op3_n),
|
.op1_out(op1_n), .op2_out(op2_n), .op2_direct(op2_dr), .op3_out(op3_n),
|
.intr(intr), .int_v(int_src), .rd(rd), .ack(ack));
|
.intr(intr), .int_v(int_src), .rd(rd), .ack(ack), .istb(istb), .istb_o(istb_o),
|
|
.iack_i(iack_i));
|
|
|
//
|
//
|
// serial interface
|
// serial interface
|
oc8051_uart oc8051_uatr1 (.clk(clk), .rst(rst), .bit_in(desCy), .rd_addr(rd_addr),
|
oc8051_uart oc8051_uatr1 (.clk(clk), .rst(rst), .bit_in(desCy), .rd_addr(rd_addr),
|
.data_in(des1), .wr(wr_r), .wr_bit(bit_addr_r), .wr_addr(wr_addr),
|
.data_in(des1), .wr(wr_r), .wr_bit(bit_addr_r), .wr_addr(wr_addr),
|
