| Line 131... |
Line 131... |
//alu_op_r alu operation (registerd)
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//alu_op_r alu operation (registerd)
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//psw_set write to psw or not; from decoder to psw (through register)
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//psw_set write to psw or not; from decoder to psw (through register)
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wire [3:0] alu_op, alu_op_r; wire [1:0] psw_set, psw_set_r;
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wire [3:0] alu_op, alu_op_r; wire [1:0] psw_set, psw_set_r;
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//
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//
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// immediate1, immediate1_r from imediate_sel1 to alu_src1_sel1
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// immediate1_r from imediate_sel1 to alu_src1_sel1
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// immediate2, immediate2_r from imediate_sel1 to alu_src2_sel1
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// immediate2_r from imediate_sel1 to alu_src2_sel1
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// src1. src2, src2 alu sources
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// src1. src2, src2 alu sources
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// des2, des2 alu destinations
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// des2, des2 alu destinations
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// des1_r destination 1 registerd (to comp1)
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// des1_r destination 1 registerd (to comp1)
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// psw output from psw
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// psw output from psw
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// desCy carry out
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// desCy carry out
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// desAc
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// desAc
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// desOv overflow
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// desOv overflow
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// wr, wr_r write to data ram
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// wr, wr_r write to data ram
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wire [7:0] src1, src2, src3, des1, des2, des1_r, psw, psw_r;
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wire [7:0] src1, src2, src3, des1, des2, des1_r, psw, psw_r;
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wire desCy, desAc, desOv, alu_cy, wr, wr_r;
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wire desCy, desAc, desOv, alu_cy, wr, wr_r;
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wire [7:0] immediate1, immediate1_r, immediate2, immediate2_r;
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wire [7:0] immediate1_r, immediate2_r;
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//
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//
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// rd read program rom
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// rd read program rom
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// pc_wr_sel program counter write select (from decoder to pc)
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// pc_wr_sel program counter write select (from decoder to pc)
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| Line 202... |
Line 202... |
oc8051_reg8 oc8051_reg8_op3(.clk(clk), .rst(rst), .din(op3_n), .dout(op3_nr));
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oc8051_reg8 oc8051_reg8_op3(.clk(clk), .rst(rst), .din(op3_n), .dout(op3_nr));
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//oc8051_reg5 oc8051_reg5_rn(.clk(clk), .rst(rst), .din({psw[4:3], op1_n[2:0]}), .dout(rn_r));
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//oc8051_reg5 oc8051_reg5_rn(.clk(clk), .rst(rst), .din({psw[4:3], op1_n[2:0]}), .dout(rn_r));
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oc8051_reg4 oc8051_reg4_alu_op(.clk(clk), .rst(rst), .din(alu_op), .dout(alu_op_r));
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oc8051_reg4 oc8051_reg4_alu_op(.clk(clk), .rst(rst), .din(alu_op), .dout(alu_op_r));
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oc8051_reg8 oc8051_reg8_imm1(.clk(clk), .rst(rst), .din(immediate1), .dout(immediate1_r));
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oc8051_reg8 oc8051_reg8_imm2(.clk(clk), .rst(rst), .din(immediate2), .dout(immediate2_r));
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oc8051_reg1 oc8051_reg1_bit_addr(.clk(clk), .rst(rst), .din(bit_addr), .dout(bit_addr_r));
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oc8051_reg1 oc8051_reg1_bit_addr(.clk(clk), .rst(rst), .din(bit_addr), .dout(bit_addr_r));
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oc8051_reg1 oc8051_reg1_wad2(.clk(clk), .rst(rst), .din(wad2), .dout(wad2_r));
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oc8051_reg1 oc8051_reg1_wad2(.clk(clk), .rst(rst), .din(wad2), .dout(wad2_r));
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oc8051_reg8 oc8051_reg8_des1(.clk(clk), .rst(rst), .din(des1), .dout(des1_r));
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oc8051_reg8 oc8051_reg8_des1(.clk(clk), .rst(rst), .din(des1), .dout(des1_r));
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oc8051_reg2 oc8051_reg2_cy(.clk(clk), .rst(rst), .din(cy_sel), .dout(cy_sel_r));
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oc8051_reg2 oc8051_reg2_cy(.clk(clk), .rst(rst), .din(cy_sel), .dout(cy_sel_r));
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| Line 248... |
Line 246... |
.desAc(desAc), .desOv(desOv), .bit_in(bit_out));
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.desAc(desAc), .desOv(desOv), .bit_in(bit_out));
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//
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//
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//
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//
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oc8051_immediate_sel oc8051_immediate_sel1(.sel(imm_sel), .op1(op1_n), .op2(op2_n),
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oc8051_immediate_sel oc8051_immediate_sel1(.clk(clr), .rst(rst), .sel(imm_sel), .op1(op1_n), .op2(op2_n),
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.op3(op3_n), .pch(pc_hi_r), .pcl(pc[7:0]), .out1(immediate1), .out2(immediate2));
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.op3(op3_n), .pch(pc_hi_r), .pcl(pc[7:0]), .out1(immediate1_r), .out2(immediate2_r));
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//
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//
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//data ram
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//data ram
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oc8051_ram_top oc8051_ram_top1(.clk(clk), .rst(rst), .rd_addr(rd_addr), .rd_data(ram_data),
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oc8051_ram_top oc8051_ram_top1(.clk(clk), .rst(rst), .rd_addr(rd_addr), .rd_data(ram_data),
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.wr_addr(wr_addr), .bit_addr(bit_addr), .wr_data(des1), .wr(wr_r),
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.wr_addr(wr_addr), .bit_addr(bit_addr), .wr_data(des1), .wr(wr_r),
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