| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2003/01/13 14:14:41 simont
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// replace some modules
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//
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// Revision 1.9 2002/09/30 17:33:59 simont
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// Revision 1.9 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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//
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//
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//
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//
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| Line 53... |
Line 56... |
`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,
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module oc8051_uart (rst, clk,
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rxd, txd, intr, t1_ow);
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bit_in, data_in,
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rd_addr, wr_addr,
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input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;
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bit_out, data_out,
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input [7:0] rd_addr, data_in, wr_addr;
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wr, wr_bit,
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rxd, txd,
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output txd, intr, bit_out;
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intr,
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brate2, t1_ow, pres_ow,
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rclk, tclk);
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input rst,
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clk,
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bit_in,
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wr,
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rxd,
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wr_bit,
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t1_ow,
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brate2,
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pres_ow,
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rclk,
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tclk;
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input [7:0] rd_addr,
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data_in,
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wr_addr;
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output txd,
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intr,
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bit_out;
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output [7:0] data_out;
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output [7:0] data_out;
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reg txd, bit_out;
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reg /*txd, */bit_out;
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reg [7:0] data_out;
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reg [7:0] data_out;
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reg tr_start, trans, trans_buf, t1_ow_buf;
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reg t1_ow_buf;
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reg [5:0] smod_cnt_r, smod_cnt_t;
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//reg tr_start, trans, trans_buf, t1_ow_buf;
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reg receive, receive_buf, rxd_buf, r_int;
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//reg [5:0] smod_cnt_r, smod_cnt_t;
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//reg receive, receive_buf, rxd_buf, r_int;
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//
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//
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reg [7:0] sbuf_rxd, sbuf_txd, scon, pcon;
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reg [7:0] /*sbuf_rxd, sbuf_txd, */scon, pcon;
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reg [10:0] sbuf_rxd_tmp;
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//reg [10:0] sbuf_rxd_tmp;
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//
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//
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//tr_count trancive counter
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//tr_count trancive counter
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//re_count receive counter
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//re_count receive counter
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reg [3:0] tr_count, re_count, re_count_buff;
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//reg [3:0] tr_count, re_count, re_count_buff;
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reg txd,
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trans,
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receive,
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tx_done,
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rx_done,
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rxd_r,
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shift_tr,
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shift_re;
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reg [1:0] rx_sam;
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reg [3:0] tr_count,
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re_count;
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reg [7:0] sbuf_rxd;
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reg [11:0] sbuf_rxd_tmp;
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reg [12:0] sbuf_txd;
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assign intr = scon[1] | scon [0];
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assign intr = scon[1] | scon [0];
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//
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//
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//serial port control register
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//serial port control register
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//
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//
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wire ren, tb8, rb8, ri;
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assign ren = scon[4];
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assign tb8 = scon[3];
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assign rb8 = scon[2];
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assign ri = scon[0];
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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scon <= #1 `OC8051_RST_SCON;
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scon <= #1 `OC8051_RST_SCON;
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else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
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else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
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scon <= #1 data_in;
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scon <= #1 data_in;
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else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
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else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
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scon[wr_addr[2:0]] <= #1 bit_in;
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scon[wr_addr[2:0]] <= #1 bit_in;
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else if ((trans_buf) & !(trans))
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else if (tx_done)
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scon[1] <= #1 1'b1;
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scon[1] <= #1 1'b1;
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else if ((receive_buf) & !(receive) & !(sbuf_rxd_tmp[0])) begin
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else if (!rx_done) begin
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case (scon[7:6])
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if (scon[7:6]==2'b00) begin
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2'b00: scon[0] <= #1 1'b1;
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scon[0] <= #1 1'b1;
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default: begin
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end else if ((sbuf_rxd_tmp[11]) | !(scon[5])) begin
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if ((sbuf_rxd_tmp[9]) | !(scon[5])) scon[0] <= #1 1'b1;
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scon[0] <= #1 1'b1;
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scon[2] <= #1 sbuf_rxd_tmp[9];
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scon[2] <= #1 sbuf_rxd_tmp[11];
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end
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end else
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endcase
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scon[2] <= #1 sbuf_rxd_tmp[11];
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end
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end
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end
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end
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//
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//
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//serial port buffer (transmit)
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//power control register
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//
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//
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wire smod;
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assign smod = pcon[7];
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst)
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sbuf_txd <= #1 `OC8051_RST_SBUF;
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begin
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tr_start <= #1 1'b0;
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pcon <= #1 `OC8051_RST_PCON;
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end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
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end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
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sbuf_txd <= #1 data_in;
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pcon <= #1 data_in;
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tr_start <= #1 1'b1;
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end else tr_start <= #1 1'b0;
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end
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end
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//
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//
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// transmit
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//serial port buffer (transmit)
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//
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//
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wire wr_sbuf;
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assign wr_sbuf = (wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit);
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
|
if (rst) begin
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txd <= #1 1'b1;
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txd <= #1 1'b1;
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tr_count <= #1 4'd0;
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tr_count <= #1 4'd0;
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trans <= #1 1'b0;
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trans <= #1 1'b0;
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smod_cnt_t <= #1 6'h0;
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sbuf_txd <= #1 11'h00;
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tx_done <= #1 1'b0;
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//
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//
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// start transmiting
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// start transmiting
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//
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//
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end else if (tr_start) begin
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end else if (wr_sbuf) begin
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case (scon[7:6])
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case (scon[7:6])
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2'b00: begin // mode 0
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2'b00: begin // mode 0
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txd <= #1 sbuf_txd[0];
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sbuf_txd <= #1 {3'b001, data_in};
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tr_count <= #1 4'd1;
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end
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end
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2'b10: begin
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2'b01: begin // mode 1
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txd <= #1 1'b0;
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sbuf_txd <= #1 {2'b01, data_in, 1'b0};
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tr_count <= #1 4'd0;
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end
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end
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default: begin // mode 1 and mode 3
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default: begin // mode 2 and mode 3
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tr_count <= #1 4'b1111;
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sbuf_txd <= #1 {1'b1, tb8, data_in, 1'b0};
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end
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end
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endcase
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endcase
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trans <= #1 1'b1;
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trans <= #1 1'b1;
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smod_cnt_t <= #1 6'h0;
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tr_count <= #1 4'd0;
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tx_done <= #1 1'b0;
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//
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//
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// transmiting/
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// transmiting
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//
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//
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end else if (trans)
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end else if (trans & (scon[7:6] == 2'b00) & pres_ow) // mode 0
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begin
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case (scon[7:6])
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2'b00: begin //mode 0
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if (smod_cnt_t == 6'd12) begin
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if (tr_count==4'd8)
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begin
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begin
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if (~|sbuf_txd[10:1]) begin
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trans <= #1 1'b0;
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tx_done <= #1 1'b1;
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end else begin
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{sbuf_txd, txd} <= #1 {1'b0, sbuf_txd};
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tx_done <= #1 1'b0;
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end
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end else if (trans & (scon[7:6] != 2'b00) & shift_tr) begin // mode 1, 2, 3
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tr_count <= #1 tr_count + 4'd1;
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if (~|tr_count) begin
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if (~|sbuf_txd[10:0]) begin
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trans <= #1 1'b0;
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trans <= #1 1'b0;
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tx_done <= #1 1'b1;
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txd <= #1 1'b1;
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txd <= #1 1'b1;
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end else begin
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end else begin
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txd <= #1 sbuf_txd[tr_count];
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{sbuf_txd, txd} <= #1 {1'b0, sbuf_txd};
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tr_count <= #1 tr_count + 4'b1;
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tx_done <= #1 1'b0;
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end
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end
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smod_cnt_t <= #1 6'h0;
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end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
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end
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end
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2'b01: begin // mode 1
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end else if (!trans) begin
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if ((t1_ow) & !(t1_ow_buf))
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txd <= #1 1'b1;
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begin
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tx_done <= #1 1'b0;
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if (((pcon[7]) & (smod_cnt_t == 6'd15))| (!(pcon[7]) & (smod_cnt_t==6'd31)))
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begin
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case (tr_count)
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4'd8: txd <= #1 1'b1; // stop bit
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4'd9: trans <= #1 1'b0;
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4'b1111: txd <= #1 1'b0; //start bit
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default: txd <= #1 sbuf_txd[tr_count];
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endcase
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tr_count <= #1 tr_count + 4'b1;
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smod_cnt_t <= #1 6'h0;
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end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
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end
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end
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end
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end
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2'b10: begin // mode 2
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//
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//
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// if smod (pcon[7]) is 1 count to 4 else count to 6
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//
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//
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if (((pcon[7]) & (smod_cnt_t==6'd31)) | (!(pcon[7]) & (smod_cnt_t==6'd63))) begin
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reg sc_clk_tr, smod_clk_tr;
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case (tr_count)
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always @(brate2 or t1_ow or t1_ow_buf or scon[7:6] or tclk)
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4'd8: begin
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begin
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txd <= #1 scon[3];
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if (scon[7:6]==8'b10) begin //mode 2
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end
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sc_clk_tr = 1'b1;
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4'd9: begin
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end else if (tclk) begin //
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txd <= #1 1'b1; //stop bit
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sc_clk_tr = brate2;
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end else begin //
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sc_clk_tr = !t1_ow_buf & t1_ow;
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end
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end
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4'd10: begin
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trans <= #1 1'b0;
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end
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end
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default: begin
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always @(posedge clk or posedge rst)
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txd <= #1 sbuf_txd[tr_count];
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end
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endcase
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tr_count <= #1 tr_count+1'b1;
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smod_cnt_t <= #1 6'h00;
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end else begin
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smod_cnt_t <= #1 smod_cnt_t + 6'h01;
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end
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end
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default: begin // mode 3
|
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if ((t1_ow) & !(t1_ow_buf))
|
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begin
|
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if (((pcon[7]) & (smod_cnt_t == 6'd15))| (!(pcon[7]) & (smod_cnt_t==6'd31)))
|
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begin
|
begin
|
case (tr_count)
|
if (rst) begin
|
4'd8: begin
|
smod_clk_tr <= #1 1'b0;
|
txd <= #1 scon[3];
|
shift_tr <= #1 1'b0;
|
end
|
end else if (sc_clk_tr) begin
|
4'd9: begin
|
if (smod) begin
|
txd <= #1 1'b1; //stop bit
|
shift_tr <= #1 1'b1;
|
end
|
end else begin
|
4'd10: begin
|
shift_tr <= #1 smod_clk_tr;
|
trans <= #1 1'b0;
|
smod_clk_tr <= #1 !smod_clk_tr;
|
end
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|
4'b1111: txd <= #1 1'b0; //start bit
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|
default: begin
|
|
txd <= #1 sbuf_txd[tr_count];
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|
end
|
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endcase
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tr_count <= #1 tr_count+1'b1;
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smod_cnt_t <= #1 6'h00;
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|
end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
|
|
end
|
end
|
|
end else begin
|
|
shift_tr <= #1 1'b0;
|
end
|
end
|
endcase
|
|
end else
|
|
txd <= #1 1'b1;
|
|
end
|
end
|
|
|
//
|
/*
|
//power control register
|
//
|
//
|
// transmit
|
always @(posedge clk or posedge rst)
|
//
|
begin
|
always @(posedge clk or posedge rst)
|
if (rst)
|
begin
|
begin
|
if (rst) begin
|
pcon <= #1 `OC8051_RST_PCON;
|
txd <= #1 1'b1;
|
end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
|
tr_count <= #1 4'd0;
|
pcon <= #1 data_in;
|
trans <= #1 1'b0;
|
end
|
smod_cnt_t <= #1 6'h0;
|
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//
|
|
// start transmiting
|
|
//
|
|
end else if (tr_start) begin
|
|
case (scon[7:6])
|
|
2'b00: begin // mode 0
|
|
txd <= #1 sbuf_txd[0];
|
|
tr_count <= #1 4'd1;
|
|
end
|
|
2'b10: begin
|
|
txd <= #1 1'b0;
|
|
tr_count <= #1 4'd0;
|
|
end
|
|
default: begin // mode 1 and mode 3
|
|
tr_count <= #1 4'b1111;
|
|
end
|
|
endcase
|
|
trans <= #1 1'b1;
|
|
smod_cnt_t <= #1 6'h0;
|
|
//
|
|
// transmiting/
|
|
//
|
|
end else if (trans)
|
|
begin
|
|
case (scon[7:6])
|
|
2'b00: begin //mode 0
|
|
if (smod_cnt_t == 6'd12) begin
|
|
if (tr_count==4'd8)
|
|
begin
|
|
trans <= #1 1'b0;
|
|
txd <= #1 1'b1;
|
|
end else begin
|
|
txd <= #1 sbuf_txd[tr_count];
|
|
tr_count <= #1 tr_count + 4'b1;
|
|
end
|
|
smod_cnt_t <= #1 6'h0;
|
|
end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
|
|
end
|
|
2'b01: begin // mode 1
|
|
if ((t1_ow) & !(t1_ow_buf))
|
|
begin
|
|
if (((pcon[7]) & (smod_cnt_t == 6'd15))| (!(pcon[7]) & (smod_cnt_t==6'd31)))
|
|
begin
|
|
case (tr_count)
|
|
4'd8: txd <= #1 1'b1; // stop bit
|
|
4'd9: trans <= #1 1'b0;
|
|
4'b1111: txd <= #1 1'b0; //start bit
|
|
default: txd <= #1 sbuf_txd[tr_count];
|
|
endcase
|
|
tr_count <= #1 tr_count + 4'b1;
|
|
smod_cnt_t <= #1 6'h0;
|
|
end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
|
|
end
|
|
end
|
|
2'b10: begin // mode 2
|
|
//
|
|
// if smod (pcon[7]) is 1 count to 4 else count to 6
|
|
//
|
|
if (((pcon[7]) & (smod_cnt_t==6'd31)) | (!(pcon[7]) & (smod_cnt_t==6'd63))) begin
|
|
case (tr_count)
|
|
4'd8: begin
|
|
txd <= #1 scon[3];
|
|
end
|
|
4'd9: begin
|
|
txd <= #1 1'b1; //stop bit
|
|
end
|
|
4'd10: begin
|
|
trans <= #1 1'b0;
|
|
end
|
|
|
|
default: begin
|
|
txd <= #1 sbuf_txd[tr_count];
|
|
end
|
|
endcase
|
|
tr_count <= #1 tr_count+1'b1;
|
|
smod_cnt_t <= #1 6'h00;
|
|
end else begin
|
|
smod_cnt_t <= #1 smod_cnt_t + 6'h01;
|
|
end
|
|
end
|
|
default: begin // mode 3
|
|
if ((t1_ow) & !(t1_ow_buf))
|
|
begin
|
|
if (((pcon[7]) & (smod_cnt_t == 6'd15))| (!(pcon[7]) & (smod_cnt_t==6'd31)))
|
|
begin
|
|
case (tr_count)
|
|
4'd8: begin
|
|
txd <= #1 scon[3];
|
|
end
|
|
4'd9: begin
|
|
txd <= #1 1'b1; //stop bit
|
|
end
|
|
4'd10: begin
|
|
trans <= #1 1'b0;
|
|
end
|
|
4'b1111: txd <= #1 1'b0; //start bit
|
|
default: begin
|
|
txd <= #1 sbuf_txd[tr_count];
|
|
end
|
|
endcase
|
|
tr_count <= #1 tr_count+1'b1;
|
|
smod_cnt_t <= #1 6'h00;
|
|
end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
|
|
end
|
|
end
|
|
endcase
|
|
end else
|
|
txd <= #1 1'b1;
|
|
end
|
|
*/
|
|
|
//
|
//
|
//serial port buffer (receive)
|
//serial port buffer (receive)
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
re_count <= #1 4'd0;
|
re_count <= #1 4'd0;
|
receive <= #1 1'b0;
|
receive <= #1 1'b0;
|
sbuf_rxd <= #1 8'h00;
|
sbuf_rxd <= #1 8'h00;
|
sbuf_rxd_tmp <= #1 11'd0;
|
sbuf_rxd_tmp <= #1 12'd0;
|
smod_cnt_r <= #1 6'h00;
|
rx_done <= #1 1'b1;
|
r_int <= #1 1'b0;
|
rxd_r <= #1 1'b1;
|
end else if (receive) begin
|
rx_sam <= #1 2'b00;
|
case (scon[7:6])
|
end else if (!rx_done) begin
|
2'b00: begin // mode 0
|
|
if (smod_cnt_r==6'd12) begin
|
|
if (re_count==4'd8) begin
|
|
receive <= #1 1'b0;
|
receive <= #1 1'b0;
|
r_int <= #1 1'b1;
|
rx_done <= #1 1'b1;
|
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
|
// if (scon[7:6]==2'b00) begin
|
end else begin
|
sbuf_rxd <= #1 sbuf_rxd_tmp[10:3];
|
sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;
|
// end else begin
|
r_int <= #1 1'b0;
|
// sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
|
end
|
// end
|
|
end else if (receive & (scon[7:6]==2'b00) & pres_ow) begin //mode 0
|
|
{sbuf_rxd_tmp, rx_done} <= #1 {rxd, sbuf_rxd_tmp};
|
|
end else if (receive & (scon[7:6]!=2'b00) & shift_re) begin //mode 1, 2, 3
|
re_count <= #1 re_count + 4'd1;
|
re_count <= #1 re_count + 4'd1;
|
smod_cnt_r <= #1 6'h00;
|
case (re_count)
|
end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
|
4'h7: rx_sam[0] <= #1 rxd;
|
end
|
4'h8: rx_sam[1] <= #1 rxd;
|
2'b01: begin // mode 1
|
4'h9: begin
|
if ((t1_ow) & !(t1_ow_buf))
|
{sbuf_rxd_tmp, rx_done} <= #1 {(rxd==rx_sam[0] ? rxd : rx_sam[1]), sbuf_rxd_tmp};
|
begin
|
|
if (((pcon[7]) & (smod_cnt_r == 6'd15))| (!(pcon[7]) & (smod_cnt_r==6'd31)))
|
|
begin
|
|
r_int <= #1 1'b0;
|
|
re_count <= #1 re_count + 4'd1;
|
|
smod_cnt_r <= #1 6'h00;
|
|
sbuf_rxd_tmp[re_count_buff] <= #1 rxd;
|
|
if ((re_count==4'd0) && (rxd))
|
|
receive <= #1 1'b0;
|
|
|
|
end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
|
|
end else begin
|
|
r_int <= #1 1'b1;
|
|
if (re_count == 4'd10)
|
|
begin
|
|
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
|
|
receive <= #1 1'b0;
|
|
r_int <= #1 1'b1;
|
|
end else r_int <= #1 1'b0;
|
|
end
|
end
|
|
endcase
|
|
//
|
|
//start receiving
|
|
//
|
|
end else if (scon[7:6]==2'b00) begin //start mode 0
|
|
rx_done <= #1 1'b1;
|
|
if (ren && !ri && !receive) begin
|
|
receive <= #1 1'b1;
|
|
sbuf_rxd_tmp <= #1 10'h0ff;
|
end
|
end
|
2'b10: begin // mode 2
|
end else if (ren & shift_re) begin
|
if (((pcon[7]) & (smod_cnt_r==6'd31)) | (!(pcon[7]) & (smod_cnt_r==6'd63))) begin
|
rxd_r <= #1 rxd;
|
r_int <= #1 1'b0;
|
rx_done <= #1 1'b1;
|
re_count <= #1 re_count + 4'd1;
|
re_count <= #1 4'h0;
|
smod_cnt_r <= #1 6'h00;
|
receive <= #1 (rxd_r & !rxd);
|
sbuf_rxd_tmp[re_count_buff] <= #1 rxd;
|
sbuf_rxd_tmp <= #1 10'h1ff;
|
re_count <= #1 re_count + 4'd1;
|
|
end else begin
|
|
smod_cnt_r <= #1 smod_cnt_r + 6'h1;
|
|
if (re_count==4'd11) begin
|
|
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
|
|
r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
|
|
receive <= #1 1'b0;
|
|
end else
|
end else
|
r_int <= #1 1'b0;
|
rx_done <= #1 1'b1;
|
end
|
end
|
end
|
|
default: begin // mode 3
|
//
|
if ((t1_ow) & !(t1_ow_buf))
|
//
|
begin
|
reg sc_clk_re, smod_clk_re;
|
if (((pcon[7]) & (smod_cnt_r == 6'd15))| (!(pcon[7]) & (smod_cnt_r==6'd31)))
|
always @(brate2 or t1_ow or t1_ow_buf or scon[7:6] or rclk)
|
begin
|
begin
|
sbuf_rxd_tmp[re_count] <= #1 rxd;
|
if (scon[7:6]==8'b10) begin //mode 2
|
r_int <= #1 1'b0;
|
sc_clk_re = 1'b1;
|
re_count <= #1 re_count + 4'd1;
|
end else if (rclk) begin //
|
smod_cnt_r <= #1 6'h00;
|
sc_clk_re = brate2;
|
end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
|
end else begin //
|
end else begin
|
sc_clk_re = !t1_ow_buf & t1_ow;
|
if (re_count==4'd11) begin
|
|
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
|
|
receive <= #1 1'b0;
|
|
r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
|
|
end else begin
|
|
r_int <= #1 1'b0;
|
|
end
|
|
end
|
end
|
end
|
end
|
endcase
|
|
|
always @(posedge clk or posedge rst)
|
|
begin
|
|
if (rst) begin
|
|
smod_clk_re <= #1 1'b0;
|
|
shift_re <= #1 1'b0;
|
|
end else if (sc_clk_re) begin
|
|
if (smod) begin
|
|
shift_re <= #1 1'b1;
|
end else begin
|
end else begin
|
case (scon[7:6])
|
shift_re <= #1 smod_clk_re;
|
2'b00: begin
|
smod_clk_re <= #1 !smod_clk_re;
|
if ((scon[4]) && !(scon[0]) && !(r_int)) begin
|
|
receive <= #1 1'b1;
|
|
smod_cnt_r <= #1 6'h6;
|
|
end
|
|
end
|
|
2'b10: begin
|
|
if ((scon[4]) && !(rxd)) begin
|
|
receive <= #1 1'b1;
|
|
if (pcon[7])
|
|
smod_cnt_r <= #1 6'd15;
|
|
else smod_cnt_r <= #1 6'd31;
|
|
end
|
end
|
end
|
end else begin
|
default: begin
|
shift_re <= #1 1'b0;
|
if ((scon[4]) && (!rxd)) begin
|
|
if (pcon[7])
|
|
smod_cnt_r <= #1 6'd7;
|
|
else smod_cnt_r <= #1 6'd15;
|
|
receive <= #1 1'b1;
|
|
end
|
end
|
end
|
end
|
endcase
|
|
|
|
sbuf_rxd_tmp <= #1 11'd0;
|
|
re_count <= #1 4'd0;
|
/*
|
r_int <= #1 1'b0;
|
always @(posedge clk or posedge rst)
|
end
|
begin
|
end
|
if (rst) begin
|
|
re_count <= #1 4'd0;
|
|
receive <= #1 1'b0;
|
|
sbuf_rxd <= #1 8'h00;
|
|
sbuf_rxd_tmp <= #1 11'd0;
|
|
smod_cnt_r <= #1 6'h00;
|
|
r_int <= #1 1'b0;
|
|
end else if (receive) begin
|
|
case (scon[7:6])
|
|
2'b00: begin // mode 0
|
|
if (smod_cnt_r==6'd12) begin
|
|
if (re_count==4'd8) begin
|
|
receive <= #1 1'b0;
|
|
r_int <= #1 1'b1;
|
|
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
|
|
end else begin
|
|
sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;
|
|
r_int <= #1 1'b0;
|
|
end
|
|
re_count <= #1 re_count + 4'd1;
|
|
smod_cnt_r <= #1 6'h00;
|
|
end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
|
|
end
|
|
2'b01: begin // mode 1
|
|
if ((t1_ow) & !(t1_ow_buf))
|
|
begin
|
|
if (((pcon[7]) & (smod_cnt_r == 6'd15))| (!(pcon[7]) & (smod_cnt_r==6'd31)))
|
|
begin
|
|
r_int <= #1 1'b0;
|
|
re_count <= #1 re_count + 4'd1;
|
|
smod_cnt_r <= #1 6'h00;
|
|
sbuf_rxd_tmp[re_count_buff] <= #1 rxd;
|
|
if ((re_count==4'd0) && (rxd))
|
|
receive <= #1 1'b0;
|
|
|
|
end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
|
|
end else begin
|
|
r_int <= #1 1'b1;
|
|
if (re_count == 4'd10)
|
|
begin
|
|
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
|
|
receive <= #1 1'b0;
|
|
r_int <= #1 1'b1;
|
|
end else r_int <= #1 1'b0;
|
|
end
|
|
end
|
|
2'b10: begin // mode 2
|
|
if (((pcon[7]) & (smod_cnt_r==6'd31)) | (!(pcon[7]) & (smod_cnt_r==6'd63))) begin
|
|
r_int <= #1 1'b0;
|
|
re_count <= #1 re_count + 4'd1;
|
|
smod_cnt_r <= #1 6'h00;
|
|
sbuf_rxd_tmp[re_count_buff] <= #1 rxd;
|
|
re_count <= #1 re_count + 4'd1;
|
|
end else begin
|
|
smod_cnt_r <= #1 smod_cnt_r + 6'h1;
|
|
if (re_count==4'd11) begin
|
|
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
|
|
r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
|
|
receive <= #1 1'b0;
|
|
end else
|
|
r_int <= #1 1'b0;
|
|
end
|
|
end
|
|
default: begin // mode 3
|
|
if ((t1_ow) & !(t1_ow_buf))
|
|
begin
|
|
if (((pcon[7]) & (smod_cnt_r == 6'd15))| (!(pcon[7]) & (smod_cnt_r==6'd31)))
|
|
begin
|
|
sbuf_rxd_tmp[re_count] <= #1 rxd;
|
|
r_int <= #1 1'b0;
|
|
re_count <= #1 re_count + 4'd1;
|
|
smod_cnt_r <= #1 6'h00;
|
|
end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
|
|
end else begin
|
|
if (re_count==4'd11) begin
|
|
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
|
|
receive <= #1 1'b0;
|
|
r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
|
|
end else begin
|
|
r_int <= #1 1'b0;
|
|
end
|
|
end
|
|
end
|
|
endcase
|
|
end else begin
|
|
case (scon[7:6])
|
|
2'b00: begin
|
|
if ((scon[4]) && !(scon[0]) && !(r_int)) begin
|
|
receive <= #1 1'b1;
|
|
smod_cnt_r <= #1 6'h6;
|
|
end
|
|
end
|
|
2'b10: begin
|
|
if ((scon[4]) && !(rxd)) begin
|
|
receive <= #1 1'b1;
|
|
if (pcon[7])
|
|
smod_cnt_r <= #1 6'd15;
|
|
else smod_cnt_r <= #1 6'd31;
|
|
end
|
|
end
|
|
default: begin
|
|
if ((scon[4]) && (!rxd)) begin
|
|
if (pcon[7])
|
|
smod_cnt_r <= #1 6'd7;
|
|
else smod_cnt_r <= #1 6'd15;
|
|
receive <= #1 1'b1;
|
|
end
|
|
end
|
|
endcase
|
|
|
|
sbuf_rxd_tmp <= #1 11'd0;
|
|
re_count <= #1 4'd0;
|
|
r_int <= #1 1'b0;
|
|
end
|
|
end
|
|
*/
|
|
|
//
|
//
|
//
|
//
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
| Line 393... |
Line 606... |
|
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
trans_buf <= #1 1'b0;
|
// trans_buf <= #1 1'b0;
|
receive_buf <= #1 1'b0;
|
// receive_buf <= #1 1'b0;
|
t1_ow_buf <= #1 1'b0;
|
t1_ow_buf <= #1 1'b0;
|
rxd_buf <= #1 1'b0;
|
// rxd_buf <= #1 1'b0;
|
end else begin
|
end else begin
|
trans_buf <= #1 trans;
|
// trans_buf <= #1 trans;
|
receive_buf <= #1 receive;
|
// receive_buf <= #1 receive;
|
t1_ow_buf <= #1 t1_ow;
|
t1_ow_buf <= #1 t1_ow;
|
rxd_buf <= #1 rxd;
|
// rxd_buf <= #1 rxd;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) bit_out <= #1 1'b0;
|
if (rst) bit_out <= #1 1'b0;
|
else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
|
else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
|
bit_out <= #1 bit_in;
|
bit_out <= #1 bit_in;
|
end else
|
end else
|
bit_out <= #1 scon[rd_addr[2:0]];
|
bit_out <= #1 scon[rd_addr[2:0]];
|
end
|
end
|
|
|
always @(posedge clk or posedge rst)
|
/*
|
if (rst)
|
always @(posedge clk or posedge rst)
|
re_count_buff <= #1 4'h4;
|
if (rst)
|
else re_count_buff <= #1 re_count;
|
re_count_buff <= #1 4'h4;
|
|
else re_count_buff <= #1 re_count;
|
|
*/
|
|
|
endmodule
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
