| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.11 2003/04/07 13:29:16 simont
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// change uart to meet timing.
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//
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// Revision 1.10 2003/01/13 14:14:41 simont
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// Revision 1.10 2003/01/13 14:14:41 simont
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// replace some modules
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// replace some modules
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//
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//
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// Revision 1.9 2002/09/30 17:33:59 simont
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// Revision 1.9 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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| Line 58... |
Line 61... |
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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|
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module oc8051_uart (rst, clk,
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module oc8051_uart (rst, clk,
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bit_in, data_in,
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bit_in, data_in,
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rd_addr, wr_addr,
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wr_addr,
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bit_out, data_out,
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wr, wr_bit,
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wr, wr_bit,
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rxd, txd,
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rxd, txd,
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intr,
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intr,
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brate2, t1_ow, pres_ow,
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brate2, t1_ow, pres_ow,
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rclk, tclk);
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rclk, tclk,
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//registers
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scon, pcon, sbuf);
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input rst,
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input rst,
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clk,
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clk,
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bit_in,
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bit_in,
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wr,
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wr,
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| Line 77... |
Line 81... |
t1_ow,
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t1_ow,
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brate2,
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brate2,
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pres_ow,
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pres_ow,
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rclk,
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rclk,
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tclk;
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tclk;
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input [7:0] rd_addr,
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input [7:0] data_in,
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data_in,
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wr_addr;
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wr_addr;
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output txd,
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output txd,
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intr,
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intr;
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bit_out;
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output [7:0] scon,
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output [7:0] data_out;
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pcon,
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sbuf;
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reg /*txd, */bit_out;
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reg [7:0] data_out;
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reg t1_ow_buf;
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reg t1_ow_buf;
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//reg tr_start, trans, trans_buf, t1_ow_buf;
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//
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//reg [5:0] smod_cnt_r, smod_cnt_t;
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reg [7:0] scon, pcon;
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//reg receive, receive_buf, rxd_buf, r_int;
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//
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reg [7:0] /*sbuf_rxd, sbuf_txd, */scon, pcon;
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//reg [10:0] sbuf_rxd_tmp;
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//
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//tr_count trancive counter
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//re_count receive counter
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//reg [3:0] tr_count, re_count, re_count_buff;
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reg txd,
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reg txd,
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trans,
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trans,
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receive,
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receive,
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| Line 117... |
Line 111... |
re_count;
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re_count;
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reg [7:0] sbuf_rxd;
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reg [7:0] sbuf_rxd;
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reg [11:0] sbuf_rxd_tmp;
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reg [11:0] sbuf_rxd_tmp;
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reg [12:0] sbuf_txd;
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reg [12:0] sbuf_txd;
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assign sbuf = sbuf_rxd;
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assign intr = scon[1] | scon [0];
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assign intr = scon[1] | scon [0];
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|
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//
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//
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//serial port control register
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//serial port control register
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//
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//
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| Line 259... |
Line 253... |
end else begin
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end else begin
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shift_tr <= #1 1'b0;
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shift_tr <= #1 1'b0;
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end
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end
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end
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end
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/*
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//
|
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// transmit
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//
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always @(posedge clk or posedge rst)
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begin
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if (rst) begin
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txd <= #1 1'b1;
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tr_count <= #1 4'd0;
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trans <= #1 1'b0;
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smod_cnt_t <= #1 6'h0;
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//
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// start transmiting
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//
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end else if (tr_start) begin
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case (scon[7:6])
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2'b00: begin // mode 0
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txd <= #1 sbuf_txd[0];
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tr_count <= #1 4'd1;
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end
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2'b10: begin
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txd <= #1 1'b0;
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tr_count <= #1 4'd0;
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end
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default: begin // mode 1 and mode 3
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tr_count <= #1 4'b1111;
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end
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endcase
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trans <= #1 1'b1;
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smod_cnt_t <= #1 6'h0;
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//
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// transmiting/
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//
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end else if (trans)
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begin
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case (scon[7:6])
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2'b00: begin //mode 0
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if (smod_cnt_t == 6'd12) begin
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if (tr_count==4'd8)
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begin
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trans <= #1 1'b0;
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txd <= #1 1'b1;
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end else begin
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txd <= #1 sbuf_txd[tr_count];
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tr_count <= #1 tr_count + 4'b1;
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end
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smod_cnt_t <= #1 6'h0;
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end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
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end
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2'b01: begin // mode 1
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if ((t1_ow) & !(t1_ow_buf))
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begin
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if (((pcon[7]) & (smod_cnt_t == 6'd15))| (!(pcon[7]) & (smod_cnt_t==6'd31)))
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begin
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case (tr_count)
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4'd8: txd <= #1 1'b1; // stop bit
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4'd9: trans <= #1 1'b0;
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4'b1111: txd <= #1 1'b0; //start bit
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default: txd <= #1 sbuf_txd[tr_count];
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endcase
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tr_count <= #1 tr_count + 4'b1;
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smod_cnt_t <= #1 6'h0;
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end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
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end
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end
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2'b10: begin // mode 2
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//
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// if smod (pcon[7]) is 1 count to 4 else count to 6
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//
|
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if (((pcon[7]) & (smod_cnt_t==6'd31)) | (!(pcon[7]) & (smod_cnt_t==6'd63))) begin
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case (tr_count)
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4'd8: begin
|
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txd <= #1 scon[3];
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end
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4'd9: begin
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txd <= #1 1'b1; //stop bit
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end
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4'd10: begin
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trans <= #1 1'b0;
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end
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default: begin
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txd <= #1 sbuf_txd[tr_count];
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end
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endcase
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tr_count <= #1 tr_count+1'b1;
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smod_cnt_t <= #1 6'h00;
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end else begin
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smod_cnt_t <= #1 smod_cnt_t + 6'h01;
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end
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end
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default: begin // mode 3
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if ((t1_ow) & !(t1_ow_buf))
|
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begin
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if (((pcon[7]) & (smod_cnt_t == 6'd15))| (!(pcon[7]) & (smod_cnt_t==6'd31)))
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begin
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case (tr_count)
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4'd8: begin
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txd <= #1 scon[3];
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end
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4'd9: begin
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txd <= #1 1'b1; //stop bit
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end
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4'd10: begin
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trans <= #1 1'b0;
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end
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4'b1111: txd <= #1 1'b0; //start bit
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default: begin
|
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txd <= #1 sbuf_txd[tr_count];
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end
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endcase
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tr_count <= #1 tr_count+1'b1;
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smod_cnt_t <= #1 6'h00;
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end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
|
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end
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end
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endcase
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end else
|
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txd <= #1 1'b1;
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end
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*/
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//
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//
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//serial port buffer (receive)
|
//serial port buffer (receive)
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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| Line 397... |
Line 270... |
rxd_r <= #1 1'b1;
|
rxd_r <= #1 1'b1;
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rx_sam <= #1 2'b00;
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rx_sam <= #1 2'b00;
|
end else if (!rx_done) begin
|
end else if (!rx_done) begin
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receive <= #1 1'b0;
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receive <= #1 1'b0;
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rx_done <= #1 1'b1;
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rx_done <= #1 1'b1;
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// if (scon[7:6]==2'b00) begin
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sbuf_rxd <= #1 sbuf_rxd_tmp[10:3];
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sbuf_rxd <= #1 sbuf_rxd_tmp[10:3];
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// end else begin
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// sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
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// end
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end else if (receive & (scon[7:6]==2'b00) & pres_ow) begin //mode 0
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end else if (receive & (scon[7:6]==2'b00) & pres_ow) begin //mode 0
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{sbuf_rxd_tmp, rx_done} <= #1 {rxd, sbuf_rxd_tmp};
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{sbuf_rxd_tmp, rx_done} <= #1 {rxd, sbuf_rxd_tmp};
|
end else if (receive & (scon[7:6]!=2'b00) & shift_re) begin //mode 1, 2, 3
|
end else if (receive & (scon[7:6]!=2'b00) & shift_re) begin //mode 1, 2, 3
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re_count <= #1 re_count + 4'd1;
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re_count <= #1 re_count + 4'd1;
|
case (re_count)
|
case (re_count)
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| Line 464... |
Line 333... |
shift_re <= #1 1'b0;
|
shift_re <= #1 1'b0;
|
end
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end
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end
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end
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|
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/*
|
|
always @(posedge clk or posedge rst)
|
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begin
|
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if (rst) begin
|
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re_count <= #1 4'd0;
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receive <= #1 1'b0;
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sbuf_rxd <= #1 8'h00;
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sbuf_rxd_tmp <= #1 11'd0;
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smod_cnt_r <= #1 6'h00;
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r_int <= #1 1'b0;
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end else if (receive) begin
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case (scon[7:6])
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2'b00: begin // mode 0
|
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if (smod_cnt_r==6'd12) begin
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if (re_count==4'd8) begin
|
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receive <= #1 1'b0;
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r_int <= #1 1'b1;
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sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
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end else begin
|
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sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;
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r_int <= #1 1'b0;
|
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end
|
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re_count <= #1 re_count + 4'd1;
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smod_cnt_r <= #1 6'h00;
|
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end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
|
|
end
|
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2'b01: begin // mode 1
|
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if ((t1_ow) & !(t1_ow_buf))
|
|
begin
|
|
if (((pcon[7]) & (smod_cnt_r == 6'd15))| (!(pcon[7]) & (smod_cnt_r==6'd31)))
|
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begin
|
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r_int <= #1 1'b0;
|
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re_count <= #1 re_count + 4'd1;
|
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smod_cnt_r <= #1 6'h00;
|
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sbuf_rxd_tmp[re_count_buff] <= #1 rxd;
|
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if ((re_count==4'd0) && (rxd))
|
|
receive <= #1 1'b0;
|
|
|
|
end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
|
|
end else begin
|
|
r_int <= #1 1'b1;
|
|
if (re_count == 4'd10)
|
|
begin
|
|
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
|
|
receive <= #1 1'b0;
|
|
r_int <= #1 1'b1;
|
|
end else r_int <= #1 1'b0;
|
|
end
|
|
end
|
|
2'b10: begin // mode 2
|
|
if (((pcon[7]) & (smod_cnt_r==6'd31)) | (!(pcon[7]) & (smod_cnt_r==6'd63))) begin
|
|
r_int <= #1 1'b0;
|
|
re_count <= #1 re_count + 4'd1;
|
|
smod_cnt_r <= #1 6'h00;
|
|
sbuf_rxd_tmp[re_count_buff] <= #1 rxd;
|
|
re_count <= #1 re_count + 4'd1;
|
|
end else begin
|
|
smod_cnt_r <= #1 smod_cnt_r + 6'h1;
|
|
if (re_count==4'd11) begin
|
|
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
|
|
r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
|
|
receive <= #1 1'b0;
|
|
end else
|
|
r_int <= #1 1'b0;
|
|
end
|
|
end
|
|
default: begin // mode 3
|
|
if ((t1_ow) & !(t1_ow_buf))
|
|
begin
|
|
if (((pcon[7]) & (smod_cnt_r == 6'd15))| (!(pcon[7]) & (smod_cnt_r==6'd31)))
|
|
begin
|
|
sbuf_rxd_tmp[re_count] <= #1 rxd;
|
|
r_int <= #1 1'b0;
|
|
re_count <= #1 re_count + 4'd1;
|
|
smod_cnt_r <= #1 6'h00;
|
|
end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
|
|
end else begin
|
|
if (re_count==4'd11) begin
|
|
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
|
|
receive <= #1 1'b0;
|
|
r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
|
|
end else begin
|
|
r_int <= #1 1'b0;
|
|
end
|
|
end
|
|
end
|
|
endcase
|
|
end else begin
|
|
case (scon[7:6])
|
|
2'b00: begin
|
|
if ((scon[4]) && !(scon[0]) && !(r_int)) begin
|
|
receive <= #1 1'b1;
|
|
smod_cnt_r <= #1 6'h6;
|
|
end
|
|
end
|
|
2'b10: begin
|
|
if ((scon[4]) && !(rxd)) begin
|
|
receive <= #1 1'b1;
|
|
if (pcon[7])
|
|
smod_cnt_r <= #1 6'd15;
|
|
else smod_cnt_r <= #1 6'd31;
|
|
end
|
|
end
|
|
default: begin
|
|
if ((scon[4]) && (!rxd)) begin
|
|
if (pcon[7])
|
|
smod_cnt_r <= #1 6'd7;
|
|
else smod_cnt_r <= #1 6'd15;
|
|
receive <= #1 1'b1;
|
|
end
|
|
end
|
|
endcase
|
|
|
|
sbuf_rxd_tmp <= #1 11'd0;
|
|
re_count <= #1 4'd0;
|
|
r_int <= #1 1'b0;
|
|
end
|
|
end
|
|
*/
|
|
|
|
//
|
//
|
//
|
//
|
//
|
//
|
always @(posedge clk or posedge rst)
|
|
begin
|
|
if (rst) data_out <= #1 8'h0;
|
|
else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) |
|
|
(wr_addr==`OC8051_SFR_SCON))) begin
|
|
data_out <= #1 data_in;
|
|
end else begin
|
|
case (rd_addr)
|
|
`OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
|
|
`OC8051_SFR_PCON: data_out <= #1 pcon;
|
|
default: data_out <= #1 scon;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
// trans_buf <= #1 1'b0;
|
|
// receive_buf <= #1 1'b0;
|
|
t1_ow_buf <= #1 1'b0;
|
t1_ow_buf <= #1 1'b0;
|
// rxd_buf <= #1 1'b0;
|
|
end else begin
|
end else begin
|
// trans_buf <= #1 trans;
|
|
// receive_buf <= #1 receive;
|
|
t1_ow_buf <= #1 t1_ow;
|
t1_ow_buf <= #1 t1_ow;
|
// rxd_buf <= #1 rxd;
|
|
end
|
end
|
end
|
end
|
|
|
|
|
always @(posedge clk or posedge rst)
|
|
begin
|
|
if (rst) bit_out <= #1 1'b0;
|
|
else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
|
|
bit_out <= #1 bit_in;
|
|
end else
|
|
bit_out <= #1 scon[rd_addr[2:0]];
|
|
end
|
|
|
|
/*
|
|
always @(posedge clk or posedge rst)
|
|
if (rst)
|
|
re_count_buff <= #1 4'h4;
|
|
else re_count_buff <= #1 re_count;
|
|
*/
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
