URL
https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_uart.v] - Diff between revs 116 and 119
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 116 |
Rev 119 |
Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.12 2003/04/07 14:58:02 simont
|
|
// change sfr's interface.
|
|
//
|
// Revision 1.11 2003/04/07 13:29:16 simont
|
// Revision 1.11 2003/04/07 13:29:16 simont
|
// change uart to meet timing.
|
// change uart to meet timing.
|
//
|
//
|
// Revision 1.10 2003/01/13 14:14:41 simont
|
// Revision 1.10 2003/01/13 14:14:41 simont
|
// replace some modules
|
// replace some modules
|
Line 109... |
Line 112... |
reg [1:0] rx_sam;
|
reg [1:0] rx_sam;
|
reg [3:0] tr_count,
|
reg [3:0] tr_count,
|
re_count;
|
re_count;
|
reg [7:0] sbuf_rxd;
|
reg [7:0] sbuf_rxd;
|
reg [11:0] sbuf_rxd_tmp;
|
reg [11:0] sbuf_rxd_tmp;
|
reg [12:0] sbuf_txd;
|
reg [10:0] sbuf_txd;
|
|
|
assign sbuf = sbuf_rxd;
|
assign sbuf = sbuf_rxd;
|
assign intr = scon[1] | scon [0];
|
assign intr = scon[1] | scon [0];
|
|
|
//
|
//
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.