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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_wb_iinterface.v] - Diff between revs 73 and 82
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| Rev 73 |
Rev 82 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/10/28 16:42:08 simont
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// initial import
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//
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// dat_o (out) data output
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// dat_o (out) data output
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// stb_i (in) strobe
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// stb_i (in) strobe
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// ack_o (out) acknowledge
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// ack_o (out) acknowledge
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// cyc_i (in) cycle
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// cyc_i (in) cycle
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input stb_i, cyc_i;
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input stb_i, cyc_i;
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input [15:0] adr_i;
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input [22:0] adr_i;
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output ack_o;
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output ack_o;
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output [31:0] dat_o;
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output [31:0] dat_o;
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//
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//
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// interface to instruction rom
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// interface to instruction rom
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// ack_i (in) acknowledge
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// ack_i (in) acknowledge
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// cyc_o (out) cycle
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// cyc_o (out) cycle
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input ack_i;
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input ack_i;
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input [31:0] dat_i;
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input [31:0] dat_i;
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output stb_o, cyc_o;
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output stb_o, cyc_o;
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output [15:0] adr_o;
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output [22:0] adr_o;
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//
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//
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// internal bufers and wires
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// internal bufers and wires
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//
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//
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reg [15:0] adr;
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reg [22:0] adr;
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reg stb;
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reg stb;
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assign ack_o = ack_i;
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assign ack_o = ack_i;
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assign dat_o = dat_i;
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assign dat_o = dat_i;
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assign stb_o = stb_i || ack_i;
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assign stb_o = stb || ack_i;
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assign cyc_o = stb_o;
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assign cyc_o = stb;
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assign adr_o = ack_i ? adr : adr_i;
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assign adr_o = ack_i ? adr : adr_i;
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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stb <= #1 1'b0;
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stb <= #1 1'b0;
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