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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/09/30 17:34:02 simont
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// prepared header
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module oc8051_fpga_top (clk, rst, int1, int2, dispout, p0_out, p1_out, p2_out, p3_out, data_out, ext_addr, rom_addr,
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module oc8051_fpga_top (clk, rst,
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rxd, txd, t0, t1);
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//
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// interrupt interface
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//
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int1, int2,
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//
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// 2x7 led display output (port 0)
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//
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dispout,
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//
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// ports
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//
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p0_out, p1_out, p2_out, p3_out,
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//
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// external instruction rom interface
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//
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ea, iadr_o, istb_o, iack_i, icyc_o, idat_i,
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//
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// external data ram interface
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//
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stb_o, cyc_o, dat_i, dat_o, adr_o, ack_i, we_o,
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//
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// serial interface
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//
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rxd, txd,
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//
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// timer/counter interface
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//
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t0, t1);
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input clk, rst, int1, int2, rxd, t0, t1;
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input clk, rst, int1, int2, ea, iack_i, ack_i, rxd, t0, t1;
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output txd;
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input [7:0] dat_i;
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input [31:0] idat_i;
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output txd, istb_o, icyc_o, stb_o, cyc_o, we_o;
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output [13:0] dispout;
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output [13:0] dispout;
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output [7:0] p0_out, p1_out, p2_out, p3_out, data_out;
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output [7:0] p0_out, p1_out, p2_out, p3_out, dat_o;
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output [15:0] ext_addr, rom_addr;
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output [15:0] adr_o, iadr_o;
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wire cstb_o, ccyc_o, cack_i;
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wire [15:0] cadr_o;
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wire [31:0] cdat_i;
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wire write, stb_o, cyc_o;
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wire [7:0] data_out, op1, op2, op3;
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wire nrst;
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wire nrst;
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assign nrst = ~rst;
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assign nrst = ~rst;
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assign op1 = 8'h00;
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oc8051_top oc8051_top_1(.rst(nrst), .clk(clk),
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assign op2 = 8'h00;
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//
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assign op3 = 8'h00;
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// interrupt interface
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//
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oc8051_top oc8051_top_1(.rst(nrst), .clk(clk), .int0(int1), .int1(int2), .ea(1'b1), .rom_addr(rom_addr), .dat_i(8'h00), .dat_o(data_out),
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.int0(int1), .int1(int2),
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.op1(op1), .op2(op2), .op3(op3), .adr_o(ext_addr), .we_o(write), .ack_i(1'b1), .stb_o(stb_o), .cyc_o(cyc_o),
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//
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.p0_in(8'hb0), .p1_in(8'hb1), .p2_in(8'hb2), .p3_in(8'hb3), .p0_out(p0_out),
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// external rom interface
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.p1_out(p1_out), .p2_out(p2_out), .p3_out(p3_out), .rxd(rxd), .txd(txd), .t0(t0), .t1(t1));
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//
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.ea(ea), .iadr_o(cadr_o), .idat_i(cdat_i), .istb_o(cstb_o), .iack_i(cack_i), .icyc_o(ccyc_o),
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//
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// external ram interface
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//
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.dat_i(dat_i), .dat_o(dat_o), .adr_o(adr_o), .we_o(we_o), .ack_i(ack_i), .stb_o(stb_o),
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.cyc_o(cyc_o),
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//
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// ports interface
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//
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.p0_in(8'hb0), .p1_in(8'hb1), .p2_in(8'hb2), .p3_in(8'hb3),
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.p0_out(p0_out), .p1_out(p1_out), .p2_out(p2_out), .p3_out(p3_out),
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//
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// serial interface
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//
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.rxd(rxd), .txd(txd),
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//
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// timer/counter interface
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//
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.t0(t0), .t1(t1));
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oc8051_icache oc8051_icache1(.rst(rst), .clk(clk),
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// oc8051
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.adr_i(cadr_o), .dat_o(cdat_i), .stb_i(cstb_o), .ack_o(cack_i),
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.cyc_i(ccyc_o),
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// external rom
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.dat_i(idat_i), .stb_o(istb_o), .adr_o(iadr_o), .ack_i(iack_i),
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.cyc_o(icyc_o));
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defparam oc8051_icache1.ADR_WIDTH = 6; // cache address wihth
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defparam oc8051_icache1.LINE_WIDTH = 3; // line address width (2 => 4x32)
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defparam oc8051_icache1.BL_NUM = 7; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
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defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
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disp disp1(.in(p0_out), .out(dispout));
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disp disp1(.in(p0_out), .out(dispout));
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endmodule
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endmodule
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