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//////////////////////////////////////////////////////////////////////
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//// ////
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//// 8051 program rom ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// ////
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//// Description ////
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//// program rom ////
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//// ////
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//// To Do: ////
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//// nothing ////
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//// ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// ver: 1
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//
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// synopsys translate_off
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`include "oc8051_timescale.v"
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// synopsys translate_on
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//`include "oc8051_defines.v"
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///
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/// created by oc8051 rom maker
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/// author: Simon Teran (simont@opencores.org)
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///
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/// source file: C:\simont\serial1.hex
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/// date: 8/16/2002
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/// time: 7:51:31 PM
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///
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module ROM32X1(O, A0, A1, A2, A3, A4); // synthesis syn_black_box syn_resources="luts=2"
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module ROM32X1(O, A0, A1, A2, A3, A4); // synthesis syn_black_box syn_resources="luts=2"
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output O;
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output O;
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input A0;
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input A0;
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input A1;
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input A1;
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input A4;
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input A4;
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endmodule
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endmodule
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//rom for 8051 processor
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//rom for 8051 processor
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module oc8051_rom (clk, rst, addr, data1, data2, data3);
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module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
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input clk, rst;
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parameter INT_ROM_WID= 7;
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input rst, clk;
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input [15:0] addr;
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input [15:0] addr;
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output ea_int;
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output [7:0] data1, data2, data3;
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output [7:0] data1, data2, data3;
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reg [7:0] data1, data2, data3;
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reg [4:0] addr01;
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reg [4:0] addr01;
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reg [7:0] data1, data2, data3;
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wire ea;
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wire [15:0] addr_rst;
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wire [15:0] addr_rst;
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wire [7:0] int_data0, int_data1, int_data2, int_data3;
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wire [7:0] int_data0, int_data1, int_data2, int_data3;
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assign ea = | addr[15:INT_ROM_WID];
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assign ea_int = ! ea;
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assign addr_rst = rst ? 16'h0000 : addr;
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assign addr_rst = rst ? 16'h0000 : addr;
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rom0 rom_0 (.a(addr01), .o(int_data0));
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rom0 rom_0 (.a(addr01), .o(int_data0));
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rom1 rom_1 (.a(addr01), .o(int_data1));
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rom1 rom_1 (.a(addr01), .o(int_data1));
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rom2 rom_2 (.a(addr_rst[6:2]), .o(int_data2));
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rom2 rom_2 (.a(addr_rst[6:2]), .o(int_data2));
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rom3 rom_3 (.a(addr_rst[6:2]), .o(int_data3));
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rom3 rom_3 (.a(addr_rst[6:2]), .o(int_data3));
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always @(addr_rst)
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always @(addr_rst)
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begin
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begin
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if (addr_rst[1])
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if (addr_rst[1])
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addr01= addr_rst[6:2]+5'b00001;
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addr01= addr_rst[6:2]+ 5'h1;
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else
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else
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addr01= addr_rst[6:2];
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addr01= addr_rst[6:2];
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end
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end
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//
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//
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// always read tree bits in row
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// always read tree bits in row
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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case(addr[1:0])
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case(addr[1:0])
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2'b00: begin
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2'd0: begin
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data1 <= #1 int_data0;
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data1 <= #1 int_data0;
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data2 <= #1 int_data1;
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data2 <= #1 int_data1;
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data3 <= #1 int_data2;
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data3 <= #1 int_data2;
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end
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end
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2'b01:begin
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2'd1: begin
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data1 <= #1 int_data1;
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data1 <= #1 int_data1;
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data2 <= #1 int_data2;
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data2 <= #1 int_data2;
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data3 <= #1 int_data3;
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data3 <= #1 int_data3;
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end
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end
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2'b10:begin
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2'd2: begin
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data1 <= #1 int_data2;
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data1 <= #1 int_data2;
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data2 <= #1 int_data3;
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data2 <= #1 int_data3;
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data3 <= #1 int_data0;
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data3 <= #1 int_data0;
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end
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end
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2'b11:begin
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2'd3: begin
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data1 <= #1 int_data3;
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data1 <= #1 int_data3;
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data2 <= #1 int_data0;
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data2 <= #1 int_data0;
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data3 <= #1 int_data1;
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data3 <= #1 int_data1;
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end
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end
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default: begin
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default: begin
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//rom0
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//rom0
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module rom0 (o,a);
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module rom0 (o,a);
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input [4:0] a;
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input [4:0] a;
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output [7:0] o;
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output [7:0] o;
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ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00003810" */;
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ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00002c01" */;
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ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=08047212" */;
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ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001800" */;
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ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=04003e00" */;
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ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000600" */;
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ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00043412" */;
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ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00002800" */;
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ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0c023c10" */;
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ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00002400" */;
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ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0c063f12" */;
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ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001600" */;
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ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=04063d10" */;
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ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000600" */;
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ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000634b2" */;
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ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00002a00" */;
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endmodule
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endmodule
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//rom1
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//rom1
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module rom1 (o,a);
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module rom1 (o,a);
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input [4:0] a;
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input [4:0] a;
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output [7:0] o;
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output [7:0] o;
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ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=040061c4" */;
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ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00002600" */;
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ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00061100" */;
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ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00003000" */;
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ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00100094" */;
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ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000601" */;
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ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00027292" */;
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ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000400" */;
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ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00123256" */;
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ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00003a00" */;
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ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00147096" */;
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ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00002a01" */;
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ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00107096" */;
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ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001200" */;
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ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00006880" */;
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ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001400" */;
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endmodule
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endmodule
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//rom2
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//rom2
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module rom2 (o,a);
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module rom2 (o,a);
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input [4:0] a;
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input [4:0] a;
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output [7:0] o;
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output [7:0] o;
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ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02101c53" */;
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ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000800" */;
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ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00023040" */;
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ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001000" */;
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ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02005261" */;
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ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001800" */;
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ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02023360" */;
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ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001200" */;
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ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02005801" */;
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ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000e00" */;
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ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02023241" */;
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ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000c00" */;
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ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02023201" */;
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ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000800" */;
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ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00023224" */;
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ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001200" */;
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endmodule
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endmodule
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//rom3
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//rom3
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module rom3 (o,a);
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module rom3 (o,a);
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input [4:0] a;
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input [4:0] a;
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output [7:0] o;
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output [7:0] o;
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ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02100b16" */;
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ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001c00" */;
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ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02200604" */;
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ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000155" */;
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ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02103416" */;
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ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001400" */;
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ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02100846" */;
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ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000800" */;
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ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00331c33" */;
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ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001555" */;
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ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0033381a" */;
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ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001555" */;
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ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0013181a" */;
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ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001600" */;
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ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000061" */;
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ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000800" */;
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endmodule
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endmodule
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