| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.14 2003/06/05 12:54:38 simont
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// remove dumpvars.
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//
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// Revision 1.13 2003/06/05 11:13:39 simont
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// Revision 1.13 2003/06/05 11:13:39 simont
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// add FREQ paremeter.
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// add FREQ paremeter.
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//
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//
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// Revision 1.12 2003/04/16 09:55:56 simont
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// Revision 1.12 2003/04/16 09:55:56 simont
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// add support for external rom from xilinx ramb4
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// add support for external rom from xilinx ramb4
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| Line 312... |
Line 315... |
clk = 0;
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clk = 0;
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forever #DELAY clk <= ~clk;
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forever #DELAY clk <= ~clk;
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end
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end
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always @(ext_addr or write or stb_o or data_out)
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initial
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$readmemh("../../../bench/vec/oc8051_test.vec", buff);
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initial
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$readmemb("../oc8051_ea.in", ea);
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initial num= 0;
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always @(p0_out or p1_out or p2_out)
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begin
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if ({p0_out, p1_out, p2_out} != buff[num])
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begin
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begin
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$display("time ",$time, " faulire: mismatch on ports in step %d", num);
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if ((ext_addr==16'h0010) & write & stb_o) begin
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$display(" p0_out %h", p0_out, " p1_out %h", p1_out, " p2_out %h", p2_out);
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if (data_out==8'h7f) begin
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$display(" testvecp %h", buff[num]);
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$display("");
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$display(" p_out %h%h%h", p0_out, p1_out, p2_out);
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$display("time ",$time, " Passed");
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#22
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$finish;
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$finish;
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end
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else begin
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end else begin
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$display("time ",$time, " step %d", num, ": pass");
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num = num+1;
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if (buff[num]===24'hxxxxxx)
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begin
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$display("");
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$display("");
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$display(" Done!");
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$display("time ",$time," Error: %h", data_out);
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$finish;
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$finish;
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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