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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/10/17 19:00:50 simont
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// add external rom
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//
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// Revision 1.4 2002/09/30 17:33:58 simont
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// Revision 1.4 2002/09/30 17:33:58 simont
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// prepared header
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// prepared header
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "oc8051_defines.v"
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module oc8051_tb;
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module oc8051_tb;
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reg rst, clk;
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reg rst, clk;
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reg [15:0] pc_in;
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reg [15:0] pc_in;
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reg [7:0] p0_in, p1_in, p2_in;
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reg [7:0] p0_in, p1_in, p2_in;
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reg ea [1:0];
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reg ea [1:0];
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integer num;
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integer num;
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//
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// oc8051 controller
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//
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oc8051_top oc8051_top_1(.rst(rst), .clk(clk), .int0(int0), .int1(int1),
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oc8051_top oc8051_top_1(.rst(rst), .clk(clk), .int0(int0), .int1(int1),
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.dat_i(data_in), .dat_o(data_out),
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.dat_i(data_in), .dat_o(data_out),
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.adr_o(ext_addr), .iadr_o(iadr_o), .istb_o(istb_o), .iack_i(iack_i),
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.adr_o(ext_addr), .iadr_o(iadr_o), .istb_o(istb_o), .iack_i(iack_i),
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.icyc_o(icyc_o), .we_o(write), .p0_in(p0_in),
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.icyc_o(icyc_o), .we_o(write), .p0_in(p0_in),
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.ack_i(ack_i), .stb_o(stb_o), .cyc_o(cyc_o),
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.ack_i(ack_i), .stb_o(stb_o), .cyc_o(cyc_o),
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.p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in), .p0_out(p0_out), .p1_out(p1_out),
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.p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in), .p0_out(p0_out), .p1_out(p1_out),
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.p2_out(p2_out), .p3_out(p3_out), .idat_i(idat_i), .ea(ea[0]),
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.p2_out(p2_out), .p3_out(p3_out), .idat_i(idat_i), .ea(ea[0]),
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.rxd(rxd), .txd(txd), .t0(t0), .t1(t1));
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.rxd(rxd), .txd(txd), .t0(t0), .t1(t1));
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//
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// external data ram
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//
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oc8051_xram oc8051_xram1 (.clk(clk), .rst(rst), .wr(write_xram), .addr(ext_addr), .data_in(data_out), .data_out(data_out_xram), .ack(ack_xram), .stb(stb_o));
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oc8051_xram oc8051_xram1 (.clk(clk), .rst(rst), .wr(write_xram), .addr(ext_addr), .data_in(data_out), .data_out(data_out_xram), .ack(ack_xram), .stb(stb_o));
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defparam oc8051_xram1.DELAY = 2;
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//
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// external uart
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//
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oc8051_uart_test oc8051_uart_test1(.clk(clk), .rst(rst), .addr(ext_addr[7:0]), .wr(write_uart),
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oc8051_uart_test oc8051_uart_test1(.clk(clk), .rst(rst), .addr(ext_addr[7:0]), .wr(write_uart),
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.wr_bit(p3_out[0]), .data_in(data_out), .data_out(data_out_uart), .bit_out(bit_out), .rxd(txd),
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.wr_bit(p3_out[0]), .data_in(data_out), .data_out(data_out_uart), .bit_out(bit_out), .rxd(txd),
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.txd(rxd), .ow(p3_out[1]), .intr(int_uart), .stb(stb_o), .ack(ack_uart));
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.txd(rxd), .ow(p3_out[1]), .intr(int_uart), .stb(stb_o), .ack(ack_uart));
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//
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// exteranl program rom
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//
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// cache
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//
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//
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`ifdef OC8051_CACHE
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wire istb_i, icyc_i, iack_o;
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wire [15:0] iadr_i;
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wire [31:0] idat_o;
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oc8051_icache oc8051_icache1(.rst(rst), .clk(clk),
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// oc8051
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.adr_i(iadr_o), .dat_o(idat_i), .stb_i(istb_o), .ack_o(iack_i),
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.cyc_i(icyc_o),
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// external rom
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.dat_i(idat_o), .stb_o(istb_i), .adr_o(iadr_i), .ack_i(iack_o),
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.cyc_o(icyc_i));
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_i), .data(idat_o),
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.stb_i(istb_i), .cyc_i(icyc_i), .ack_o(iack_o));
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defparam oc8051_icache1.ADR_WIDTH = 6; // cache address wihth
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defparam oc8051_icache1.LINE_WIDTH = 3; // line address width (2 => 4x32)
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defparam oc8051_icache1.BL_NUM = 7; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
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defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
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//
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// no cache
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//
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`else
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_o), .data(idat_i),
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_o), .data(idat_i),
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.stb_i(istb_o), .cyc_i(icyc_o), .ack_o(iack_i));
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.stb_i(istb_o), .cyc_i(icyc_o), .ack_o(iack_i));
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`endif
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//
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//
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//
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defparam oc8051_xrom1.DELAY = 5;
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assign write_xram = p3_out[7] & write;
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assign write_xram = p3_out[7] & write;
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assign write_uart = !p3_out[7] & write;
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assign write_uart = !p3_out[7] & write;
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assign data_in = p3_out[7] ? data_out_xram : data_out_uart;
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assign data_in = p3_out[7] ? data_out_xram : data_out_uart;
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assign ack_i = p3_out[7] ? ack_xram : ack_uart;
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assign ack_i = p3_out[7] ? ack_xram : ack_uart;
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p0_in = 8'h00;
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p0_in = 8'h00;
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p1_in = 8'h00;
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p1_in = 8'h00;
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p2_in = 8'h00;
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p2_in = 8'h00;
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#22
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#22
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rst = 1'b0;
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rst = 1'b0;
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//#2000000
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//#444000
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//#4444000
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#7000000
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#7000000
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$display("time ",$time, "\n faulire: end of time\n \n");
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$display("time ",$time, "\n faulire: end of time\n \n");
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$finish;
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$finish;
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end
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end
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