| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/10/24 13:36:53 simont
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// add instruction cache and DELAY parameters for external ram, rom
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//
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// Revision 1.5 2002/10/17 19:00:50 simont
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// Revision 1.5 2002/10/17 19:00:50 simont
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// add external rom
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// add external rom
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//
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//
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// Revision 1.4 2002/09/30 17:33:58 simont
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// Revision 1.4 2002/09/30 17:33:58 simont
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// prepared header
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// prepared header
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| Line 112... |
Line 115... |
// exteranl program rom
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// exteranl program rom
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//
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//
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// cache
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// cache
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//
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//
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//
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//
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`ifdef OC8051_CACHE
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wire istb_i, icyc_i, iack_o;
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wire istb_i, icyc_i, iack_o;
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wire [15:0] iadr_i;
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wire [15:0] iadr_i;
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wire [31:0] idat_o;
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wire [31:0] idat_o;
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`ifdef OC8051_CACHE
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oc8051_icache oc8051_icache1(.rst(rst), .clk(clk),
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oc8051_icache oc8051_icache1(.rst(rst), .clk(clk),
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// oc8051
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// oc8051
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.adr_i(iadr_o), .dat_o(idat_i), .stb_i(istb_o), .ack_o(iack_i),
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.adr_i(iadr_o), .dat_o(idat_i), .stb_i(istb_o), .ack_o(iack_i),
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.cyc_i(icyc_o),
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.cyc_i(icyc_o),
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// external rom
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// external rom
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| Line 131... |
Line 134... |
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_i), .data(idat_o),
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_i), .data(idat_o),
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.stb_i(istb_i), .cyc_i(icyc_i), .ack_o(iack_o));
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.stb_i(istb_i), .cyc_i(icyc_i), .ack_o(iack_o));
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defparam oc8051_icache1.ADR_WIDTH = 6; // cache address wihth
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defparam oc8051_icache1.ADR_WIDTH = 6; // cache address wihth
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defparam oc8051_icache1.LINE_WIDTH = 3; // line address width (2 => 4x32)
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defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)
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defparam oc8051_icache1.BL_NUM = 7; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
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defparam oc8051_icache1.BL_NUM = 15; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
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defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
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defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
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//
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//
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// no cache
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// no cache
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//
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//
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`else
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`else
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_o), .data(idat_i),
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oc8051_wb_iinterface oc8051_wb_iinterface(.rst(rst), .clk(clk),
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.stb_i(istb_o), .cyc_i(icyc_o), .ack_o(iack_i));
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// oc8051
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.adr_i(iadr_o), .dat_o(idat_i), .stb_i(istb_o), .ack_o(iack_i),
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.cyc_i(icyc_o),
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// external rom
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.dat_i(idat_o), .stb_o(istb_i), .adr_o(iadr_i), .ack_i(iack_o),
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.cyc_o(icyc_i));
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_i), .data(idat_o),
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.stb_i(istb_i), .cyc_i(icyc_i), .ack_o(iack_o));
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`endif
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`endif
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//
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//
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//
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//
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//
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//
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defparam oc8051_xrom1.DELAY = 5;
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defparam oc8051_xrom1.DELAY = 5;
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//
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// test wb interface
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//
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reg [31:0] log_file;
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initial
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begin
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log_file = $fopen("log_file");
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$fdisplay(log_file, "file open");
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end
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// cache/cpu to instruction rom
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//
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WB_BUS_MON wb_bus_mon1(.CLK_I(clk), .RST_I(rst), .ACK_I(iack_o), .ADDR_O({16'h0000, iadr_i}), .CYC_O(icyc_i),
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.DAT_I(idat_o), .DAT_O(32'd0), .ERR_I(1'b0), .RTY_I(1'b0), .SEL_O(4'b0000), .STB_O(istb_i),
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.WE_O(1'b0), .TAG_I(4'h0), .TAG_O(4'h0), .CAB_O(1'b0), .log_file_desc(log_file));
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// cpu to data ram
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//
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WB_BUS_MON wb_bus_mon3(.CLK_I(clk), .RST_I(rst), .ACK_I(ack_i), .ADDR_O({16'h0000, ext_addr}), .CYC_O(cyc_o),
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.DAT_I({24'h000000, data_in}), .DAT_O({24'h000000, data_out}), .ERR_I(1'b0), .RTY_I(1'b0), .SEL_O(4'b0000), .STB_O(stb_o),
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.WE_O(write), .TAG_I(4'h0), .TAG_O(4'h0), .CAB_O(1'b0), .log_file_desc(log_file));
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//
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//
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//
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//
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assign write_xram = p3_out[7] & write;
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assign write_xram = p3_out[7] & write;
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assign write_uart = !p3_out[7] & write;
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assign write_uart = !p3_out[7] & write;
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assign data_in = p3_out[7] ? data_out_xram : data_out_uart;
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assign data_in = p3_out[7] ? data_out_xram : data_out_uart;
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| Line 177... |
Line 219... |
#22
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#22
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rst = 1'b0;
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rst = 1'b0;
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//#444000
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//#444000
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#7000000
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#7000000
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$fclose(log_file);
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$display("time ",$time, "\n faulire: end of time\n \n");
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$display("time ",$time, "\n faulire: end of time\n \n");
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$finish;
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$finish;
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end
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end
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| Line 204... |
Line 247... |
$display("time ",$time, " faulire: mismatch on ports in step %d", num);
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$display("time ",$time, " faulire: mismatch on ports in step %d", num);
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$display(" p0_out %h", p0_out, " p1_out %h", p1_out, " p2_out %h", p2_out);
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$display(" p0_out %h", p0_out, " p1_out %h", p1_out, " p2_out %h", p2_out);
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$display(" testvecp %h", buff[num]);
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$display(" testvecp %h", buff[num]);
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$display(" p_out %h%h%h", p0_out, p1_out, p2_out);
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$display(" p_out %h%h%h", p0_out, p1_out, p2_out);
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#22
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#22
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$fclose(log_file);
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$finish;
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$finish;
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end
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end
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else begin
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else begin
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$display("time ",$time, " step %d", num, ": pass");
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$display("time ",$time, " step %d", num, ": pass");
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num = num+1;
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num = num+1;
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if (buff[num]===24'hxxxxxx)
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if (buff[num]===24'hxxxxxx)
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begin
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begin
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$display("");
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$display("");
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$display(" Done!");
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$display(" Done!");
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$fclose(log_file);
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$finish;
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$finish;
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end
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end
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end
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end
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end
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end
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