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verilog ../../../bench/verilog/oc8051_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src_sel.v ../../../rtl/verilog/oc8051_alu.v ../../../rtl/verilog/oc8051_decoder.v ../../../rtl/verilog/oc8051_divide.v ../../../rtl/verilog/oc8051_multiply.v ../../../rtl/verilog/oc8051_memory_interface.v ../../../rtl/verilog/oc8051_ram_top.v ../../../sim/rtl_sim/src/verilog/oc8051_ram.v ../../../sim/rtl_sim/src/verilog/oc8051_xram.v ../../../rtl/verilog/oc8051_acc.v ../../../rtl/verilog/oc8051_comp.v ../../../rtl/verilog/oc8051_sp.v ../../../sim/rtl_sim/src/verilog/oc8051_uart_test.v ../../../sim/rtl_sim/src/verilog/oc8051_rom.v ../../../sim/rtl_sim/src/verilog/oc8051_xrom.v ../../../rtl/verilog/oc8051_dptr.v ../../../rtl/verilog/oc8051_cy_select.v ../../../rtl/verilog/oc8051_psw.v ../../../rtl/verilog/oc8051_indi_addr.v ../../../rtl/verilog/oc8051_ports.v ../../../rtl/verilog/oc8051_b_register.v ../../../rtl/verilog/oc8051_uart.v ../../../rtl/verilog/oc8051_int.v ../../../rtl/verilog/oc8051_tc.v ../../../rtl/verilog/oc8051_tc2.v ../../../rtl/verilog/oc8051_icache.v ../../../sim/rtl_sim/src/verilog/oc8051_cache_ram.v ../../../rtl/verilog/oc8051_wb_iinterface.v ../../../rtl/verilog/oc8051_sfr.v
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verilog \
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../../../bench/verilog/oc8051_tb.v \
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../../../bench/verilog/oc8051_xram.v \
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../../../bench/verilog/oc8051_uart_test.v \
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../../../bench/verilog/oc8051_xrom.v \
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../../../rtl/verilog/oc8051_top.v \
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../../../rtl/verilog/oc8051_alu_src_sel.v \
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../../../rtl/verilog/oc8051_alu.v \
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../../../rtl/verilog/oc8051_decoder.v \
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../../../rtl/verilog/oc8051_divide.v \
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../../../rtl/verilog/oc8051_multiply.v \
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../../../rtl/verilog/oc8051_memory_interface.v \
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../../../rtl/verilog/oc8051_ram_top.v \
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../../../rtl/verilog/oc8051_acc.v \
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../../../rtl/verilog/oc8051_comp.v \
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../../../rtl/verilog/oc8051_sp.v \
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../../../rtl/verilog/oc8051_dptr.v \
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../../../rtl/verilog/oc8051_cy_select.v \
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../../../rtl/verilog/oc8051_psw.v \
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../../../rtl/verilog/oc8051_indi_addr.v \
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../../../rtl/verilog/oc8051_ports.v \
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../../../rtl/verilog/oc8051_b_register.v \
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../../../rtl/verilog/oc8051_uart.v \
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../../../rtl/verilog/oc8051_int.v \
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../../../rtl/verilog/oc8051_tc.v \
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../../../rtl/verilog/oc8051_tc2.v \
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../../../rtl/verilog/oc8051_icache.v \
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../../../rtl/verilog/oc8051_wb_iinterface.v \
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../../../rtl/verilog/oc8051_sfr.v \
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../../../rtl/verilog/oc8051_ram.v \
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../../../rtl/verilog/oc8051_rom.v \
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../../../rtl/verilog/oc8051_cache_ram.v \
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../../../memory/xilinx/rom_32x1/rom_32x1.v \
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../../../memory/xilinx/ramb_521x8_dual/ramb_521x8_dual.v
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