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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [tags/] [rel_2/] [sim/] [rtl_sim/] [run/] [make_verilog] - Diff between revs 100 and 106
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| Rev 100 |
Rev 106 |
| Line 25... |
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../../../rtl/verilog/oc8051_tc.v \
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../../../rtl/verilog/oc8051_tc.v \
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../../../rtl/verilog/oc8051_tc2.v \
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../../../rtl/verilog/oc8051_tc2.v \
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../../../rtl/verilog/oc8051_icache.v \
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../../../rtl/verilog/oc8051_icache.v \
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../../../rtl/verilog/oc8051_wb_iinterface.v \
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../../../rtl/verilog/oc8051_wb_iinterface.v \
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../../../rtl/verilog/oc8051_sfr.v \
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../../../rtl/verilog/oc8051_sfr.v \
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../../../rtl/verilog/oc8051_ram.v \
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../../../rtl/verilog/oc8051_rom.v \
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../../../rtl/verilog/oc8051_rom.v \
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../../../rtl/verilog/oc8051_cache_ram.v \
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../../../rtl/verilog/oc8051_cache_ram.v \
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../../../memory/xilinx/rom_32x1/rom_32x1.v \
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../../../../common/generic_memories/rtl/verilog/generic_dpram.v
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../../../memory/xilinx/ramb_521x8_dual/ramb_521x8_dual.v
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../../../../common/generic_memories/rtl/verilog/generic_dpram.v
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