| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.11 2003/04/10 12:45:06 simont
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// defines for pherypherals added
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//
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// Revision 1.10 2003/04/03 19:20:55 simont
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// Revision 1.10 2003/04/03 19:20:55 simont
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// Remove instruction cache and wb_interface
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// Remove instruction cache and wb_interface
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//
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//
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// Revision 1.9 2003/04/02 15:08:59 simont
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// Revision 1.9 2003/04/02 15:08:59 simont
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// rename signals
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// rename signals
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| Line 76... |
Line 79... |
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module oc8051_tb;
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module oc8051_tb;
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reg rst, clk;
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reg rst, clk;
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reg [7:0] p0_in, p1_in, p2_in;
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reg [7:0] p0_in, p1_in, p2_in;
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wire [31:0] idat_i;
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wire [15:0] ext_addr, iadr_o;
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wire [15:0] ext_addr, iadr_o;
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wire write, write_xram, write_uart, txd, rxd, int_uart, int0, int1, t0, t1, bit_out, stb_o, ack_i;
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wire write, write_xram, write_uart, txd, rxd, int_uart, int0, int1, t0, t1, bit_out, stb_o, ack_i;
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wire ack_xram, ack_uart, cyc_o, iack_i, istb_o, icyc_o, t2, t2ex;
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wire ack_xram, ack_uart, cyc_o, iack_i, istb_o, icyc_o, t2, t2ex;
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wire [7:0] data_in, data_out, p0_out, p1_out, p2_out, p3_out, data_out_uart, data_out_xram, p3_in;
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wire [7:0] data_in, data_out, p0_out, p1_out, p2_out, p3_out, data_out_uart, data_out_xram, p3_in;
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wire wbi_err_i, wbd_err_i;
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wire wbi_err_i, wbd_err_i;
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`ifdef OC8051_XILINX_RAMB
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reg [31:0] idat_i;
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`else
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wire [31:0] idat_i;
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`endif
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///
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///
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/// buffer for test vectors
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/// buffer for test vectors
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///
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///
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//
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//
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| Line 164... |
Line 171... |
//
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//
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oc8051_uart_test oc8051_uart_test1(.clk(clk), .rst(rst), .addr(ext_addr[7:0]), .wr(write_uart),
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oc8051_uart_test oc8051_uart_test1(.clk(clk), .rst(rst), .addr(ext_addr[7:0]), .wr(write_uart),
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.wr_bit(p3_out[0]), .data_in(data_out), .data_out(data_out_uart), .bit_out(bit_out), .rxd(txd),
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.wr_bit(p3_out[0]), .data_in(data_out), .data_out(data_out_uart), .bit_out(bit_out), .rxd(txd),
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.txd(rxd), .ow(p3_out[1]), .intr(int_uart), .stb(stb_o), .ack(ack_uart));
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.txd(rxd), .ow(p3_out[1]), .intr(int_uart), .stb(stb_o), .ack(ack_uart));
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`ifdef OC8051_XILINX_RAMB
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`include "oc8051_rom_values.v"
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//
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//
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// exteranl program rom
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// exteranl program rom
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//
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//
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//
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// rom 0
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//
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wire [11:0] adr0, adr1;
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wire [15:0] dat0, dat1;
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assign adr0 = iadr_o[13:2] + {11'h0, iadr_o[1]};
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assign adr1 = iadr_o[13:2];
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rom_8kx16_top rom_8kx16_top_0
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(
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// WISHBONE slave
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.wb_clk_i(clk),
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.wb_rst_i(rst),
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.wb_dat_i(16'h0),
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.wb_dat_o(dat0),
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.wb_adr_i(adr0),
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.wb_sel_i(2'b11),
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.wb_we_i(1'b0),
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.wb_cyc_i(icyc_o),
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.wb_stb_i(istb_o),
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.wb_ack_o(iack_i),
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.wb_err_o(wbi_err_i)
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);
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rom_8kx16_top rom_8kx16_top_1
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(
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// WISHBONE slave
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.wb_clk_i(clk),
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.wb_rst_i(rst),
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.wb_dat_i(16'h0),
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.wb_dat_o(dat1),
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.wb_adr_i(adr1),
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.wb_sel_i(2'b11),
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.wb_we_i(1'b0),
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.wb_cyc_i(icyc_o),
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.wb_stb_i(istb_o),
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.wb_ack_o(iack_i),
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.wb_err_o(wbi_err_i)
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);
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defparam rom_8kx16_top_0.awidth = 12;
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defparam rom_8kx16_top_1.awidth = 12;
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always @(iadr_o[1:0] or dat0 or dat1)
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begin
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case (iadr_o[1:0])
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2'b00: idat_i = {8'h0, dat1[7:0], dat0};
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2'b01: idat_i = {8'h0, dat1, dat0[15:8]};
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2'b10: idat_i = {8'h0, dat0[7:0], dat1};
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default: idat_i = {8'h0, dat0, dat1[15:8]};
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endcase
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end
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`else
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_o), .data(idat_i),
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_o), .data(idat_i),
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.stb_i(istb_o), .cyc_i(icyc_o), .ack_o(iack_i));
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.stb_i(istb_o), .cyc_i(icyc_o), .ack_o(iack_i));
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defparam oc8051_xrom1.DELAY = 5;
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`endif
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//
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//
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//
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//
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//
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//
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defparam oc8051_xrom1.DELAY = 5;
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//
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//
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// test wb interface
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// test wb interface
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//
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//
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